SBL support to load PreOS and normal OS in a single boot option.
This patch tries to standardize the PreOS support.
The PreOS could be TrustyOS, PreOsChecker or others.
As long as PreOS flag is set in boot option, SBL will load and
boot PreOS before normal OS. If the preOS has specific requirement,
it could be addressed using PreOS image type.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Python 3.4 and above have deprecated imp module in favor of
importlib. This patch removed imp module usage from SBL, and
used importlib instead.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed link error for APL NOOPT build due to compiler
intrinsics functions. However, due to APL hardware requirements,
it is not feasible to fit NOOPT build into real flash. This
patch will not fix the NOOPT build error caused by code size issue.
For example, the following error might still occur for APL NOOPT
build:
Invalid the required fv image size 0xe3b0 exceeds the set fv image
size 0x6000
The APL SOC requires Stage1A to fit into 32KB. Since FSP-T will take
8KB, it only gives 24KB for SBL Stage1A code. NOOPT build will create
about 56KB for Stage1A, and it is impossible to fit into the layout.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The structure of ME_BIOS_PAYLOAD varies on silicons. So, it's moved to
silicon directory and common structures are in MeBiosPayloadDataCommon.h.
- MeBiosPayloadDataCommon.h in CommonSocPkg
- MeBiosPayloadData.h in the specific silicon package
Additionally, DEBUG_VERBOSE message level is used for HeciCore.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This allows APL target to use the common HECI library.
The APL target uses the common HeciLib from CommonSocPkg,
and overrides MeChipsetLib for Apollake specific APIs.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch did the following
1) Added common routines LocateVbtByImageId to look for VBT image using
ImageId provided by configuration data and GetVbtAddress.
2) GetVbtAddress routine will provide abstaction for all platforms
irrespective of multiple VBT or single VBT used by the platform.
3) LocateVbtByImageId routine is moved from platform local function to
common package.
4) VbtImageId configuration option defined in QEMU platform config is
moved to common configuration in CfgData_Common.yaml
5) ApolloLake VBT ID selection is now done using configuration data.
6) Added latest VBT binary for CFL, WHL is using existing VBT.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current ConfigEditor relies on the original input data format in YAML
to determine how to represent data in GUI. For example, if the data
value is HEX in YAML, then the data will be displayed in HEX format.
This patch switched to use the specified format type to reformat the
value string so that the display is always consistent with the required
format type.
It fixed#844.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added support to launch payload module on top of OsLoader.
Comparing with payload binary, payload module will utilize the API
services provided by OsLoader, so it will have smaller size. Other
than this, the concept is exactly same as normal payload. For payload
module, additional parameter is required to pass into the payload
module entry point.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted some alignment on PCI resource allocation so
that PCI resource is more efficently utilized. It aslo adjusted
the framebuffer MTRR range to match PCI resource allocation.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enables OS to allocate 64bit PCI resource on APL platform.
It will help resolve some cases where 32bit PCI resource is very
limited.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The new YAML format represented some data structure a little bit
differently from original DSC format. This patch did minor adjustment
to make the build pass on APL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
As discussed in the RFC, SBL will use YAML format for CFGDATA format
going forward. This patch converted CFGDATA files from DSC format into
YAML format for QEMU, CFL and APL platforms.
To convert existing DSC file into YAML file, please use tool:
python BootloaderCorePkg\Tools\Dsc2Yaml.py <Path to CfgDataDef.dsc>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed some ACPI issue on APL platform. When VT-d is
disabled, DMAR table should not be populated in ACPI. This patch
fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
KEY IDs are extended to include key type and sizes.
Platforms can configure corresponding RSA2048 and
RSA3072 KEY IDs. Updated tools to adjust hash type
based on key size.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch enables usage of key id for private keys
in slimboot repo. Key ids are configured in
BuildLoader and platform BoardConfig files.
SLIMBOOT_KEY_DIR is set to default folder outside
sblopen.
Generation of extrenal Keyhash OS key hash to be configured
for QEMU/CGL/APL with appropriate keys.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
The unnecessary wbinvd() is removed from the common ResetSystemLib,
and it moves to a platform specific reset routine.
Signed-off-by: Aiden Park <aiden.park@intel.com>
- Created BaseIpcLib
- Sideband Interface picked from
tianocore/edk2-platforms
branch: devel-IntelAtomProcessorE3900
commit: 181f9e6c6ccde6e3fa62278b3a8b39cfb5844a7c
- IPC Interface picked from
tianocore/edk2-platforms
branch: devel-IntelAtomProcessorE3900
commit: 181f9e6c6ccde6e3fa62278b3a8b39cfb5844a7c
- Updated Stage1BBoardInitLib.C with a test function
Signed-off-by: Andrey Vinokurtsev <avinok@gmail.com>
This patch fixed OsLoader boot from SD card issue on Intel APL CRB
borads. The SD/eMMC library was updated to follow the proper sequence
for SD card. Also platform code was updated to detect SD card and
apply SD card power using proper GPIO pins.
It fixed#729.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current APL StitchIfwi.py does not enable PDR region due to incorrect
XML option. This patch fixed this and also adjusted the default PDR
region to be 4KB to save space.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
PcdVerifiedBootHashMask is no longer used while
verification except for stage1B. Remove Hash mask and
added PcdVerifiedBootStage1B for stage1B verification.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
For APL StitchIfwi.py script, if relative path is provided for the
stitching workspace, the stitching process will error out. This
patch fixed this issue by converting the relative path to absolute
path before passing it into the stitching functions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted the memory SKU ID detection for UP2. There is
another GPIO PIN which needs to read to get a full memory SKU ID.
This has not been only tested on SKU 0 so far due ot lack of other
SKU UP2 boards.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added UP2 specific VBT table to enable both HDMI an DP
ports. The VBT from FSP repo can only support HDMI.
It fixed#651.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled APL X64 boot. In X64 mode, more heap is required
for Stage1A since it needs to build page tables. As part of it, APL
CAR region map has been re-arranged so as to save more space. This
has been tested on LeafHill CRB board.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current build only allows board to customize the DSC libraries.
It is better to allow more flexible DSC customization. This patch
enabled this capability. Board can override library, PCDs, etc.
As part of it, the old GetDscLibrary() interface will be deprecated.
Please use GetPlatformDsc() instead.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Add missing X64 MdePkg Library
This adds some missing Library from EDKII Stable201911.
- MdePkg/Library/BaseMemoryLibRepStr/X64
- MdePkg/Library/BaseSynchronizationLib/X64
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Make X64 target buildable
This is just to build X64 target - Not functional.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added UP2 board memory SKU3 support. This was enabled
by trying different memory configurations to find the working
configurations. It might not be optimal, but a good start point.
Special acknowlegement to andreyv1978 who did the enabling on his
board and contributed the code back.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Add SMI status register
Add SMI lock register
Add REG_TYPE_MMIO register type
Zero SMM HOB
Fill SMI lock info for CFL and APL platform
Signed-off-by: Guo Dong <guo.dong@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added required code flow to prepare to enable DMA
protection for APL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For APL, since VT-d is only enabled
in FspSiliconInit, it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added the VTd PMR memory protection library. It can be
used to support DMA memory protection feature later on. It also
enabled basic build on APL platform so that it can be tested as part
of the automatic build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added code to:
- Trigger FWU using sticky register in SBL Shell
- Detect FWU mode using combination of sticky register and state
machine
- Clear the trigger flag at the end of FWU
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to sync up with EDK201911 stable release, it is required
to add missing header files in the INF file. Otherwise, the build
will throw warnings. This patch added the missing headers in INF
files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are many parameter passing to AcpiPatchPssTable().
A single PSS_PARAMS structure pointer will be passed to simplify.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will allow update PSS table in a common way.
For a platform specific power calculation,
a function pointer can be provided.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL hash store has many limitations:
- Only support fixed hash size
- Only support 1:1 public key and usage mapping
- Only support build time key enrollment
This patch addressed this issue by introducing:
- Add a updatable KEYH component to hold extra key hash
- Allow append new hash entries from KEYH
- Use variable length entry for hash
- Introduce "Usage" bit mask for a key usage
This will allow using a single key to sign multiple components, or
using multiple keys to sign a single component. The built-in hash
store will only contain hash for STAGE1B, STAGE2, PAYLOAD,
PAYLOAD_FWU and MASTER public key hash. Master key hash will be used
to verify the KEYH component loaded at runtime in Stage1B. Once KEYH
is loaded, it will be appended into global hash store. The combined
hash store will be used to verify other components on the boot flow.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch updated the PayloadId detection logic on APL platform
to make it easy to understand.
The current policy is as below:
- If PayloadId CFGDATA is not AUTO, use whatever provided in CFGDATA.
- If PayloadId CFGDATA is AUTO, and GPIO based PayloadId detection
is enabled, uses GPIO level to determine the actual PayloadId to
use. (HIGH:OsLoader LOW:UEFI)
- If PayloadId CFGDATA is AUTO, and GPIO based PayloadId detection
is disabled, uses default PlatfomrId 0 (OsLoader).
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
AVX(G9) and SSE4(W7) is added to IPP crypto lib.
PcdCryptoShaOptEnabled is added to enable optimzations
in IPP SHA256 and SHA384.
Default is set to V8 (SSE3) for SHA256. ENABLE_CRYPTO_SHA_OPT has to
be configured in Platform board config files for optimizations
to be enabled.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
PcdDebugInterfaceFlags and PcdDebugOutputDeviceMask are defined
for debug devices, so removed PcdDebugInterfaceFlags.
Add a new PCD PcdDebugPortNumber to indicate the serial debug
number.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added WMI service in ACPI to provide a unified mechnism
for user to trigger a firmware update flow. New ASL methods are
defined. \DWMI.WQ00 is for read and \DWMI.WS00 is for write.
To use it from Linux (Ubuntu):
- Install acpi-call module
sudo apt install acpi-call-dkms
- Load module
sudo modprobe acpi_call
- Read trigger register value
echo '\DWMI.WQ00 0' | sudo tee /proc/acpi/call
sudo cat /proc/acpi/call
- Write trigger register value
echo '\DWMI.WS00 0 0x12' | sudo tee /proc/acpi/call
To use it in Windows:
- Open a command line window with admin right.
- Run VB script to read / write the trigger register
set Service = GetObject("winmgmts:root/wmi")
set EnumSet = Service.InstancesOf ("AcpiFirmwareCommunication")
for each Instance in EnumSet
Wscript.Echo "Current Val: " & Hex(instance.Command)
instance.Command = 1
instance.Put_()
Wscript.Echo "Set New Val: " & Hex(instance.Command)
next 'instance
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Guo Dong