There are many parameter passing to AcpiPatchPssTable().
A single PSS_PARAMS structure pointer will be passed to simplify.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will allow update PSS table in a common way.
For a platform specific power calculation,
a function pointer can be provided.
Signed-off-by: Aiden Park <aiden.park@intel.com>
- Update of comment in Fwst.aslc for coffeelake as per review comment.
- Update of comment in Boardconfig.py for qemu.
- Removal of vtf0.bsf in BootloaderCorePkg.
Signed-off-by: SM <s.m.narayanan@intel.com>
This patch added following enhancement to GenContainer script:
- Fixed python3 errors in some specific condition
- Added more error handling to notifce the user on failure
- Removed -od option and use directory of -o option instead
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In GenContainer tool auth definitions for RSA cases were
updated to include hash alg used. In current implementation
auth type is generated from hash type and private key while
container created. This patch removes hash type param
and auth type is used for hash alg generation.
Platform code to be updated as per updated auth definitions
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Configuration data blob is supported only from Bios region.
Removing CfgData in PDR as its no longer getting used.
Updated to copy signed data structure length for max supported.
Max supported is for RSA3072 size.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch does the following
1) Enable triggering firmware update from OS
2) When firmware update mode is given control, state machine
is set to capsule processing and firmware update platform
specific trigger is cleared. State machine will be used
hereafter to track firmware update
3) Created CheckStateMachine method in BoardSupportLib.c to
check state machine to see if firmware update is in progress
and set boot mode to firmware update.
4) Removed CMOS way of triggering firmware update and wrote code
to use Over-Clocking WDT Scratchpad (OC_WDT_SCRATCH) bits for
triggering firmware update
5) Update shell fwupdate command to use OC_WDT_SCRATCH bits.
6) Removed extra reset during sbl firmware update
7) Removed reset after updating configuration data update
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Hash and RSA signing parameters were hardcoded in
Crypto wrappers and secure boot libraries. This patch
address support for multiple hash and key sizes.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
Current SBL hash store has many limitations:
- Only support fixed hash size
- Only support 1:1 public key and usage mapping
- Only support build time key enrollment
This patch addressed this issue by introducing:
- Add a updatable KEYH component to hold extra key hash
- Allow append new hash entries from KEYH
- Use variable length entry for hash
- Introduce "Usage" bit mask for a key usage
This will allow using a single key to sign multiple components, or
using multiple keys to sign a single component. The built-in hash
store will only contain hash for STAGE1B, STAGE2, PAYLOAD,
PAYLOAD_FWU and MASTER public key hash. Master key hash will be used
to verify the KEYH component loaded at runtime in Stage1B. Once KEYH
is loaded, it will be appended into global hash store. The combined
hash store will be used to verify other components on the boot flow.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch updated the PayloadId detection logic on APL platform
to make it easy to understand.
The current policy is as below:
- If PayloadId CFGDATA is not AUTO, use whatever provided in CFGDATA.
- If PayloadId CFGDATA is AUTO, and GPIO based PayloadId detection
is enabled, uses GPIO level to determine the actual PayloadId to
use. (HIGH:OsLoader LOW:UEFI)
- If PayloadId CFGDATA is AUTO, and GPIO based PayloadId detection
is disabled, uses default PlatfomrId 0 (OsLoader).
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The previoius IPP library updates used UpdateSHA256V8 as default for
SHA256. It works on real platform. However, QEMU's default CPU config
does not support SSE3 instructions and will generate exception. This
patch added the UpdateSHA256Compact as default SHA256 function if no
advanced optimization flags are set. The same is applied for SHA512
functions too.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
AVX(G9) and SSE4(W7) is added to IPP crypto lib.
PcdCryptoShaOptEnabled is added to enable optimzations
in IPP SHA256 and SHA384.
Default is set to V8 (SSE3) for SHA256. ENABLE_CRYPTO_SHA_OPT has to
be configured in Platform board config files for optimizations
to be enabled.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
PcdDebugInterfaceFlags and PcdDebugOutputDeviceMask are defined
for debug devices, so removed PcdDebugInterfaceFlags.
Add a new PCD PcdDebugPortNumber to indicate the serial debug
number.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added WMI service in ACPI to provide a unified mechnism
for user to trigger a firmware update flow. New ASL methods are
defined. \DWMI.WQ00 is for read and \DWMI.WS00 is for write.
To use it from Linux (Ubuntu):
- Install acpi-call module
sudo apt install acpi-call-dkms
- Load module
sudo modprobe acpi_call
- Read trigger register value
echo '\DWMI.WQ00 0' | sudo tee /proc/acpi/call
sudo cat /proc/acpi/call
- Write trigger register value
echo '\DWMI.WS00 0 0x12' | sudo tee /proc/acpi/call
To use it in Windows:
- Open a command line window with admin right.
- Run VB script to read / write the trigger register
set Service = GetObject("winmgmts:root/wmi")
set EnumSet = Service.InstancesOf ("AcpiFirmwareCommunication")
for each Instance in EnumSet
Wscript.Echo "Current Val: " & Hex(instance.Command)
instance.Command = 1
instance.Put_()
Wscript.Echo "Set New Val: " & Hex(instance.Command)
next 'instance
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL currently set IA Untrust bit in MpInit(). It is too early for
BSP. By doing so, it blocked some register access in FSP notification
APIs. This patch moved the IA Untrust bit set for BSP to the end of
boot flow while keeping it at same location for APs.
It also fixed#466.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL calls ClearFspHob() too early. Since HOB is required
during the whole FSP life cycle. It is better to clear it at the
end after the last call. Otherwise, some previous API call will
potentically encounter issues.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This is a follow-up to the previous WOL commit. The previous
implementation is more LeafHill specific. This patch further
added configuration data to control how wake up signal is mapped
into each PCIE root port. And the ASL code has been adjusted to
utilize that info so that the code can be more generic for all
other platforms.
The current default configuration for PCIE wake signal is aligned
with LeafHill CRB board. For other borads, to enable it properly,
it is required to override the wake signal configuration using DLT.
Test has been done on LeafHill to do WOL with yocto image. It worked
as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added export sub-command support in CfgDataTool.py. It
is useful for users to export external CFGDATA from an exising
BIOS or IFWI binary file.
EX:
python BootloaderCorePkg\Tools\CfgDataTool.py export
-i Outputs\cfl\SlimBootloader.bin -o Temp
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added additional information in the GPIO CFGDATA header
structure so that the full GPIO info can be extracted out later on
by tool. This additional information including GPIO SKIP bit position,
GPIO ID position and length.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL has platform specific GetBuiltInConfigData() implementation
because the internal CFGDATA blob is embedded into Stage1B data section.
Instead, it can be put into Stage1B FV FFS file, and then use a PCD to
get the base. In this way, it can be handled directly in core code and
remove platform specific implementation.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
MRC re-init happens in next boot when an warm reset is issued in MRC
fast boot path. DRAM Initialization Scratchpad Bit is one of warm reset
detection logics, but the bit is not updated at fast boot path.
Signed-off-by: Aiden Park <aiden.park@intel.com>
OsBootOption config data provides addendum field to support multiple boot
option config data into a single boot option.
This patch updates a single boot option properly with multiple addendums.
Signed-off-by: Aiden Park <aiden.park@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
UEFIPayload uses SMM dispatch for Physical Presence (Tcg2SMM) SMI.
Updated SMI port usage in asl to trigger SMI registered for
Physical Presence operation
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
GenGpioData.py is a utility that converts
GPIO pin data from one format to other.
The formats currently supported are [h, csv, txt, dsc, dlt].
[h, csv, txt] formats are external to SBL and [dsc, dlt] formats
are known to SBL. So, this tool provides a way to convert one
of the [h, csv, txt] to [dsc, dlt] and vice-versa.
Example usage:
python GenGpioData.py -if GpioInput.csv -of dsc
python GenGpioData.py -if GpioInput.dsc -of txt
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
ConfigEditor.py tool reports a warning regarding the
incorrect Interrupt Configuration for pins on Upx boards.
Certain board's default PAD CFG values may have none of
NMI/SMI/SCI/IOAPIC set and also RXEVCFG set to Disable,
so add a corresponding option in the drop-down for IntConfig.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Currently, only absolute path is allowed in '-w' stitch_dir and '-s'
stitch_zip file. In addition, if stitch_dir is not absolute path, the
stitch tool looks for 'SBL_SOURCE' which does not exist in OS environment.
This patch allows the StitchIfwi.py tool to use relative path as well.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Added a option in CFL StitchIfwi script to pass the TPM type to
be selected for Intel FIT tool stitching.
[TEST] = Run StitchIfwi.py with -tpm=dtpm for WHL
and verify use of dTPM.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
BootPolicyManifest are required when a IFWI is
stitched with Intel BootGuard enabled. FlashMap maintains a pointer to
it so that SBL code can reach to them during execution.
This patch removes the check for its presence from IFWI images.
Test : Stitches Ok. Boots Ok.
Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
This patch is a follow-up patch of #380. If a platform disables HS400 mode,
silicon init code will configure eMMC in HS200. Other modes not in scope.
This will also fix#406.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows a board to configure XDCI mode.
By default, keep XDCI mode as PCI mode which is default value in FSP.
The mode can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 2 > Enable XDCI
If XDCI mode needs to be overrided, put new value in .dlt(delta) file.
- DEV_EN_CFG_DATA.DevEnControl2.XdciEnable | 0x0 (Disabled)
- DEV_EN_CFG_DATA.DevEnControl2.XdciEnable | 0x2 (ACPI mode)
It will fix#397 with the override value in a delta file.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch adds IPC1 device to DSDT and exposes it to OS.
The behavior can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 1 > IPC1 Enable/Disable
It also fixed#390.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch changes the default behavior of gpio pin for payload
selection, currently user configured GPIO pin being high boots
to uefi payload, modified code will boot to OS loader when GPIO pin
is high.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
power button 4 second press will cause power button override
bit to set in PM1 status register, this bit is not cleared on
reset and is causing SMI storm during booting to OS.
Power button override bit if set is cleared now in stage1b and
this fixed the SMI storm issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current code set payload id depending on the gpio settings
and user selection from configuration data. When UEFI payload is
selected using GPIO or config data, payload id is being set to
UEFI irrespective of boot mode, which cause notification function
to get called, this locks the spi which inturn fails firmware update
Modified code to set payload id only in non-firmware update boot mode.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added csme wrapper driver for csme update library.
following functionality is added in this patch
1. Boardconfig PCD option ENABLE_CSME_UPDATE is added to
enable/disable csme update support
2. Boardconfig PCD option BUILD_CSME_UPDATE_DRIVER is added
to enable/disable building csme update driver
3. If BUILD_CSME_UPDATE_DRIVER is 1, user need to create
library that inludes csme update library
this newly created library will get linked to csme update
wrapper driver providing csme update driver
4. By default ENABLE_CSME_UPDATE is set to 0
5. Revision control for input and output data structure to
update driver is not implemented and will be avaiable
in further patches.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
UPX board has different memory configurations indicated by GPIO pins.
This patch added GPIO detections for these pins and set it as BomID.
It can be used to decide which SPD data to use later on.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted power related UPD settings to BIOS
UPD values are configurable through configuration data
After these changes, CPU maximum operating frequency
increased from 3.7GHZ to 4.2GHZ on WHL.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This is to fit the size of the latest Debug UEFI Payload.
Increase the size from 0x00180000 to 0x00190000.
Signed-off-by: Aiden Park <aiden.park@intel.com>
StitchIfwi.py supports '-q' parameter to enable SPI QUAD mode.
However, it does not work as expected. When the script tries to
modify the XML file, it used 'yes' and 'no' as option values.
But it is case sensitive, and should use 'Yes' and 'No' instead.
This patch fixed this issue.
Test was done on LeafHill board and it enabled SPI QUAD mode
in IFWI after the fix. It fixed#370.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows APL and WHL(CFL) to use common header file for SPI
register access.
APL and CFL are using common SpiFlashLib and PchSpiLib, but Platform
code still refering to its own SPI registers header file.
- Remove duplicated header file
- Add common one to Silicon/CommonSocPkg
- Use SPI registers from common one in each Platform code
Signed-off-by: Aiden Park <aiden.park@intel.com>
Aiden Park