The patch adds a feature to read Dts at boot. The feature
is analogous to UEFI BIOS:
Thermal Conf -> Platform Thermal Conf -> Boot DTS Read
Specifically, the feature reads Tjunctions of PCH and CPU
and stores them as Smbios Type-28 entries.
The patch also fixes AppendSmbiosType in SmbiosInitLib:
A newly added structure should inherit the Handle from
previous Type-127 (end-of-table) structure.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch adds a platform hook function ability
in Pci Enum Lib to enable platform to perform
PCI Enum specific work-around routines.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
For non UEFI payload, SBL will install dummy SMI handler for
security concern. For UEFI payload, SMM rebasing is expected
to be done itself. This patch enabled this feature for APL and
CFL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch implemented a common method for platform to create ACPI
table dynamically. Platform can provide ACPI tempalte array through
PCD PcdAcpiTableTemplatePtr. If provided, ACPI core code will try to
call platform code to patch the table, and then install the table to
ACPI RSDT/XSDT.
It also added sample code implementation in QEMU to show case how to
do it from platform code.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This introduces an additional PCI Enumeration option.
- self._PCI_ENUM_FLAG_ALLOC_PMEM_FIRST
By deafult, the option will allocate PCI resource by ascending order
(MEM32->PMEM32->MEM64->PMEM64). If it's set to 1, by reversed order.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This adds a common IgdOpRegion library for the same APIs on TGL
and EHL platforms. Plan to include older platforms support in the v2
patch.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
Current PCI resource PCD bases are defined as fixed type. It
makes it impossible to dynamically adjust the base at runtime.
This patch changed it to be module patchable so that platform
can update when required.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This introduces a new PCD 'PcdPciResAllocTableBase' to allow a platform
to provide its specific PCI resource allocation pool at runtime.
PCI Enumerator will allocate required resources in the range.
If the PCD is not provided, a default range will be used.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL code will build pointers in E/F segment for ACPI
and SMBIOS table. On some platforms, E/F segment is not supported.
So a new configuration ENABLE_LEGACY_EF_SEG is added. When
it is enabled, SBL will not use legacy E/F segment memory.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In 64-bit operation, some PCI devices have high mmio BARs,
but 32-bit FSP can only access 32-bit memory space.
This introduces and additional PCI resource downgrade option
to downgrade all PCI devices under Bus-0.
- self._PCI_ENUM_DOWNGRADE_BUS0 = 1
Force to have 32-bit BAR for all Bus-0 devices
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added SBL python setup script. It can run on either host
or target MicroPython environment. A new PCD PcdEnableSetup is added
to control if Setup feature should be supported by core.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
FspsUpd variable made global so that it could be accessed out of
FspSilicon function.
Patchable PCD has been created for FspsUpd and Memory pool allocated.
Signed-off-by: Perni <ramesh.chandra.perni@intel.com>
FSP 2.1 introduced new requirement to use bootloader stack for FSP-M. It
will cause issue for SBL since SBL only uses a small stack in Stage1. To
address this issue, a new PCD PcdFSPMStackTop is added to control the
stack settings for FSP-M.
- If it is 0, it will not switch stack before calling FspMemoryInit API.
- If it is 0xffffffff, it will switch to the new default FSP stack
before calling FspMemoryInit API.
- For other values, it will switch to the new stack at specified value
before calling FspMemoryInit API.
This PCD will be set automatically by FSP_M_STACK_TOP variable in
BoardConfig.py file.
This code has been tested on UP Extreme board with latest FSP version.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will support PCI SR-IOV(Single Root I/O Virtualization).
- Controlled by PcdSrIovSupport (SUPPORT_SR_IOV in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will enable ARI(Alternative Routing-ID Interpretation).
- Controlled by PcdAriSupport (SUPPORT_ARI in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
PcdVerifiedBootHashMask is no longer used while
verification except for stage1B. Remove Hash mask and
added PcdVerifiedBootStage1B for stage1B verification.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
PciEnumeration() scans a single PCI root bridge currently.
The PCI_ENUM_POLICY_INFO structure will be generated at build time,
and this will allow PCI enumeration more flexible.
typedef struct {
UINT8 DowngradeIo32;// default:1
UINT8 DowngradeMem64; // default:1
UINT8 DowngradePMem64;// default:1
UINT8 Reserved;
UINT8 BusScanType; // default:0 (0: list, 1: range)
UINT8 NumOfBus; // the number of BusScanItems
UINT8 BusScanItems[0];
} PCI_ENUM_POLICY_INFO;
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows to setup Stage1 stack/data in any CAR range.
By default, the stack base offset is 0 from CarBase.
Signed-off-by: Aiden Park <aiden.park@intel.com>
HASH_STORE_TABLE is updated and HASH_STORE_DATA is added
to provide info with variable length sizes. Usage bits would
notify for multiple component/key using the same hash.
These data structure would optimize the hash store size
in storage.
PcdHashStoreSize would define the size of Hash store
to allocate in bios bootup.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
PcdDebugInterfaceFlags and PcdDebugOutputDeviceMask are defined
for debug devices, so removed PcdDebugInterfaceFlags.
Add a new PCD PcdDebugPortNumber to indicate the serial debug
number.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current SBL has platform specific GetBuiltInConfigData() implementation
because the internal CFGDATA blob is embedded into Stage1B data section.
Instead, it can be put into Stage1B FV FFS file, and then use a PCD to
get the base. In this way, it can be handled directly in core code and
remove platform specific implementation.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Split PreOsChecker in a separate file and add minimum APIs
- IsPreOsCheckerLoaded ()
- LoadPreOsChecker ()
- StartPreOsChecker ()
Token space has been changed for PcdPreOsCheckerEnabled
- gPlatformModuleTokenSpaceGuid to gPlatformCommonLibTokenSpaceGuid
- Include/Excluded PreOsChecker according to FeaturePcd
Signed-off-by: Aiden Park <aiden.park@intel.com>
OsLoader has the capability to boot a Linux kernel. However, to support
LinuxBoot type of payload, it is required to load kernel in Stage2. This
patch abstracts the standard Linux loading logic into common LinuxLib
class so that it can be linked in Stage2 or Payload such as OsLoader.
A new PcdLinuxPayloadEnabled is introduced to control if this feature
should be enabled or not.
To boot a Linux kernel from Stage2, it is required to put the command
line file and kernel image into the EPAYLOAD container during the build.
And the PayloadId CFGDATA needs to be set to 'LINX'.
For example:
python BuildLoader.py build qemu
-p OsLoader.efi::Lz4;vmlinuz:LINX:Dummy;cmdline.txt:CMDL:Dummy
vmlinuz and cmdkube.txt need to be copied to PayloadPkg/PayloadBins
folder. If kernel size cannot fit into EPAYLOAD, EPAYLOAD_SIZE in
BoardConfig.py needs to be adjusted accordingly.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Some platform might need do some platform specific init
on all the threads. So add a MP hook using a PCD.
Np impact for the platform that doesn't need this hook.
This patch also enable InSMM bit for APL.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Some OSes may require a pre-OS checker executable
to run before actually jumping to the OS. Add
support for this pre-OS checker loading & execution
as part of the OS Loader payload when it is compiled
as an FV and when ENABLE_PRE_OS_CHECKER option is
enabled in BoardConfig.py (per the following command):
SblBuild.py build <plat> -p OsLoader.Fv:LLDR:Lz4
The pre-OS checker entry point takes in a single
parameter which provides the CPU boot state that
should be loaded once jumping into the OS for the
pre-OS checker to launch after it finishes execution
(e.g. pre-OS checker does not return to Slim Bootloader).
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Smm bases for all the procs need to be relocated on the
S3 resume path (as payload is not run) for Windows boot.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current code refers hash store as "key store". It is confusing
since there is no key stored in the image at all. Instead, the
public key hash is stored. The patch renames the KeyStore
to HashStore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL has no intention to support SMI. However, on many hardware
platforms, there is no reliable way to prevent SMI from generating
through SMI IPI. In case it occurs, CPU will jump to the default
0x38000 location for execution, which exposes huge security issues.
The recommended solution is to do basic SMM base relocation and put
a dummy SMI handler (RSM) there for platform does not support SMI
disabling. In this way, the SMI will be ignored, and it also closes
the security concerns. This patch implemented basic SMM relocation.
It is under the control of a new PCD PcdSmmRebaseEnabled. By default,
it is disabled. To enable it, please set ENABLE_SMM_REBASE in
BoardConfig.py. As part of it, platform library needs to set
PcdSmramTsegBase and PcdSmramTsegSize properly in PreSiliconInit board
hook. Please take APL platform for reference.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On APL platform, all PCI MMIO range is set to UC in current
implementation. It includes graphics framebuffer MMIO. It
caused the system performance issue due to large mount of
framebuffer write access. This patch set framebuffer as
WC (WriteCombining) per recommendation to enhance system
performance.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Enable DebugAgentLib to support source level debug over serial
By default, source level debug is NOT enabled. ENABLE_SOURCE_DEBUG
needs to be set to 1 in BoardConfig.py of each Platforms.
- self.ENABLE_SOURCE_DEBUG = 1
As an initial drop, there are some limitations on APL platform.
- Stage1A does not include DebugAgentLib due to Stage1A size
limitation(32KB). Further optimization is required.
- DebugAgentLib supports ONLY POSTMEM debugging on APL currently.
Refer to EDKII Debugging:
- https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Debugging
- https://github.com/tianocore/tianocore.github.io/wiki/SourceLevelDebugPkg
Change-Id: Ia28c5470bc5755768f2b380cc1dabbcb8ee60f0d
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Additional changes for DebugAgent
- Adjust stage size depending on ENABLE_SOURCE_DEBUG Pcd value
- Add PeCoffFindAndReportImageInfo
- Fix debugger hang at Shell
Change-Id: I11b41e5ad610fcb2999e9d43e5dd8f8899e8265a
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Move PeCoffFindAndReportImageInfo() from LitePeCoffLib to DebugAgentLib
Change-Id: I2c4ab4f9561dfd0536da1820048f0e5f2660e2ab
Signed-off-by: Aiden Park <aiden.park@intel.com>
Stanley Chang