SIGN_HASH_TYPE and IPP_HASH_LIB_SUPPORTED_MASK are derived from
_SIGN_HASH. AT times only _SIGN_HASH is configured in
BoardConfig.py which causes in incorrect hash set to
respective PCDs.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This will fix an unexpected exception when AhciHcPciBase is invalid
or the PCI config space is not enabled.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL supports container header verification. If the container
signature is BOOT, it will use HASH_USAGE_PUBKEY_OS. Otherwise, it
will use HASH_USAGE_PUBKEY_CONTAINER_DEF. This patch added OEM signed
container support. If a container signature between OEM0 to OEM7 is
found, it will be verified use HASH_USAGE_PUBKEY_OEM(x) where x is 0
to 7. To add an OEM public key hash, it can be done by updating
pub_key_list in GetKeyHashList() in file BoardConfig.py.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
FSP 2.1 introduced new requirement to use bootloader stack for FSP-M. It
will cause issue for SBL since SBL only uses a small stack in Stage1. To
address this issue, a new PCD PcdFSPMStackTop is added to control the
stack settings for FSP-M.
- If it is 0, it will not switch stack before calling FspMemoryInit API.
- If it is 0xffffffff, it will switch to the new default FSP stack
before calling FspMemoryInit API.
- For other values, it will switch to the new stack at specified value
before calling FspMemoryInit API.
This PCD will be set automatically by FSP_M_STACK_TOP variable in
BoardConfig.py file.
This code has been tested on UP Extreme board with latest FSP version.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds generic functionality to
process Flash descriptor lock. It follows
Capsule Firmware update flow and interface
is updated. Command (CMDI) interface is added
to GenCapsuleFirmware which takes file with
command as input.
Sample Command format in text file input,
{FLASHDESCLOCK}
{Command2}
{Command3}
Firmware update lib handler parses high level commands
Specific command process and functionlity would be
performed by platform specific libraries.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This will support PCI SR-IOV(Single Root I/O Virtualization).
- Controlled by PcdSrIovSupport (SUPPORT_SR_IOV in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch will generate a SW smi on S3 resume path when using
UEFI payload. Handler for this Sw smi in UEFI payload will
program SMRR base and mask for BSP and all AP's.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Boot Options updated for selecting boot device as SPI.
Use the “Memory” setting in the ConfigEditor to select
SPI as boot device.
Signed-off-by: Mutha <naga.naveen.mutha@intel.com>
This will enable ARI(Alternative Routing-ID Interpretation).
- Controlled by PcdAriSupport (SUPPORT_ARI in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
Klocwork reports a potential dereferencing of a NULL
pointer. This patch addresses the issue.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Platform debug mode is extended to PCR[7]
as part of secure boot policy. Updated bit setting
to LoaderPlatformInfo for payloads to consume.
Debug mode is checked in payload.
ArchitecturalMsr.h ported fom EDK2 repo.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This will allow necessary messages to be printed to consoles.
These macros will redirect debug message to consoles.
CONSOLE_PRINT
CONSOLE_PRINT_UNICODE
These conditional macros will redirect debug message to consoles or
DEBUG(). The PrintLevel is valid only when redirected to DEBUG().
CONSOLE_PRINT_CONDITION
CONSOLE_PRINT_UNICODE_CONDITION
Signed-off-by: Aiden Park <aiden.park@intel.com>
To help debug boot performance, add a MTRR print function.
This function could be invoked multiple times with different
string to know where this MTRR data is printed.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch enhances MapMemoryRegion subroutine to
add PDP entries for mapping addresses > 4GiB.
Only 1:1 mapping is provided for Above4Gb addresses.
And linear addresses are mapped to 1GiB pages.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This issue is seen on a WHL board on X64 build when high 32-bit
BAR does not exist. In that case, MmioRead64 returns (UINT64)(-1).
To avoid this, read high 32-bit BAR only if BAR type is 64-bit
address space.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will support S3 resume path on X64 thru 16-bit waking vector.
- Port WakeUp code from EDKII
- Remove duplicated calls of FindS3Info from CpuInit
- Verified with Yocto on a WHL board
- TBD: 64-bit waking vector with supported OS
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will fix MpInit failure on X64 build.
The ApFunc() gets invalid parameters due to mismatched calling convention.
- Add EFIAPI to match calling convention
This can be verified with '-smp' option on QEMU target.
qemu-system-x86_64
-machine q35 -m 256 -nographic -serial mon:stdio
-pflash Outputs/qemu/SlimBootloader.bin
-smp 255
Signed-off-by: Aiden Park <aiden.park@intel.com>
PublicKey hashes stored in HashStore use hash alg type of
PcdCompSignHash defined with Build config. In container we
support cases where hash type could differ from Sbl default
signing hash.
Adjust the hash algorithm in external KeyHashStore manifest
based on key size. Use SHA256 for size 2K and SHA384 for 3K.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Current container library cannot be used before memory is initialized
because the structure will only be initialized after memory. This
patch moved the initialization into Stage1A so that the library can be
used much earlier. The containers registered before memory will be
migrated into memory automatically post memory initialization. In this
way it avoids duplicated header authentication.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Currently BootGuard library is maintained for
every supported silicon. Most of Slimboot supported
platforms support CBnT standard. Adding to SOC common
for platforms to consume.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This will load and execute 64-bit ELF image.
- Load image from ELF program header
- 32-bit ELF on IA32 only. 64-bit ELF on X64 only
- TBD: Relocate ELF
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added support for arrow keys on PS2 numeric keypad.
The original code only supports the dedicated arrow keys.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current APL StitchIfwi.py does not enable PDR region due to incorrect
XML option. This patch fixed this and also adjusted the default PDR
region to be 4KB to save space.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In Shell FS after media initialization, the de-initialization
should be called to free all allocated memory.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Scrolling mouse in ConfigEditor with Python3 will trigger some
error message. During the scroll unit calculation, it is required
to convert float into int type. This patch fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Recent Linux kernel accepts acpi_rsdp=0x.. in kernel command line.
This will make Linux kernel look for ACPI RSDP address in the kernel
commad line first prior to in DMI or F-segment.
Signed-off-by: Aiden Park <aiden.park@intel.com>
FSP could produce a FSP boot performance HOB.
So add the capability to print FSP performance data.
Also add a PcdBootPerformanceMask to enable/disable
boot performance data print.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch simplified ingredient folder structure
required for stitchifwi. Also created a config file
with all the configuration in one file and this file
will now be input to stitchifwi
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch upgraded the LZ4 from 1.4.0 to 1.7.4. The size will
increase around 300 bytes. Performance is still very similar.
But when trying to use more recent LZ4 version 1.9, noticed
significant performance degration. So keep to 1.7.4 for now.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
If Platform code assigns 64-bit BAR address to XHCI,
get the full 64-bit address to access MMIO space.
Behavior is undefined if building IA32 and assigning
64-bit XHCI resources.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch added build hooks for boards so that each board can do
specific actions in different build phases. This patch also added
an example for QEMU to use build hook to generate new binaries into
the flash layout.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Fix XHCI library memory de-allocation issue
This patch added code to XHCI de-initialization funciton to free
all used memory.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Enhance USB De-initialization flow
This patch enhanced the USB De-initializaiton flow by trying to
call de-init functions in the full USB driver stack including XHCI,
UsbBus, UsbBot, etc.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added NVMe de-initialization function to stop the controller
and de-allocate all memory allocated.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added function UsbDeinitDevice() in UsbBusLib to free
memory allocated for all USB devices.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Correct the index reported while dumping the
PCI resource information.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Co-authored-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
PcdVerifiedBootHashMask is no longer used while
verification except for stage1B. Remove Hash mask and
added PcdVerifiedBootStage1B for stage1B verification.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch added support to report free memory resource lenghth.
It will search for all used memory pages and add them together.
The "virtual" free address will be returned to indicate the
virtual start point of the free memory top. It is virtual since the
memory allocation can be fragmented. This is just an indicator to
calculate the actual used memory size:
UsedMemSize = EndAddr - FreeAddr
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Subash Lakkimsetti