Add PchPseAicEnabled and PchUnlockGpioPads in
CfgData_Silicon.yaml file to allow modification
using Config Editor tool.
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
This patch added a new 64bit base field in the loader serial
port hob to support 64bit resource. The revision is updated
to 2. It is backward compatible with revision 1.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Pass in a pch_series param to GpioDataConvert tool
to fetch the correct gpio group info for a platform
based on the pch series.
The tool expects the platform specific config file to
implement a function vir_to_phy_grp () that returns
a BOOL value based on:
If vir_to_phy_grp = False, SBL's config has A->0, B->1 etc. mapping.
And GpioSiLib.c or GpioInitLib.c corresponding libraries will map
this virtual group #s to real physical group #s (if not same).
If vir_to_phy_grp = True, SBL's config has A->G1, B->G2 etc.
physical mapping directly, so the GpioLib library uses this as is.
GpioDataConfig.py file was added for ADL platform.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
When run as part of an automated system it's important to ensure that
any failure is reported to the calling process. Writing an error message
and then exiting indicating success leads to difficult-to-diagnose
problems.
Signed-off-by: Mike Crowe <mac@mcrowe.com>
This patch enhanced GPIO convert tool so that it can handle the
new GPIO template format.
EX:
To convert GPIO from YAML format to CSV format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
Platform\ElkhartlakeBoardPkg\CfgData\CfgData_Gpio.yaml
-of csv -o gpio.csv
To convert GPIO from CSV to YAML format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
gpio.csv -of yaml -o gpio.yaml -t new
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
1. Update VERINFO_PROJ_MINOR_VER to 3 for MR3
2. Update PSE SIZE to 0x00030000
3. Removal of PchCpuTempSensorEnable FSP UPD due
FSP update
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Increase CFG_DATABASE_SIZE due to the addition
of up6000 dlt file in SBL EHL cfgdata.
The AddConfigData funciton will return EFI_OUT_OF_RESOURCES
due to insufficient cfgdata size when TCC is enabled.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Increase epayload size to 0x00162000 for compilation
error with latest debug version of uefi-payload
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
Current GpioLib uses 2 bits from OtherSettings to
configure RxRaw field in GPIO PAD CFG DWORD 0. But
Gpio config templates are missing the option to configure
this feature. This patch adds the option in template.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added PcdAcpiProcessorIdBase to allow platform to
customize the processor ID start base within MADT APIC entry.
Current EHL and TGL declared PR00 processor object in ACPI
with unique ID value 0, but other projects used vlaue 1
instead. This patch will help fix this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are too much ERROR level debug message in GPIO library. Since
ERROR level debug message will be stored in final release binary,
it increases the image size. This patch changed the GPIO DEBUG
level to VERBOSE by default to reduce binary size. When debug is
needed, we can change the debug level in the header file to allow
more detailed info.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Removal of disabling AcSplitLock FSP UPD.
The FSP UPD is commented out due to the Yocto hang
issue previously which no longer occured.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Since the commit below was reverted
24f5aa59b5. The cache flush
need to be moved into the place where data consistency
across warm reset is required. The patch added the WBINVD
to flush the cache before "fwupdate" command issues warm
reset.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Disable the new GPIO scheme by default in dlt file
Only enable this option for kernel version 4.18.0-315
Alternatively with kernel module parameter
'module_blacklist=pinctrl_elkhartlake' will works
without enabling this GPIO scheme.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch added payload selection GPIO configuration
hardcoded GPIO pin for payload selection.
It also fixed#1196.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Co-authored-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are several config options that will be overridden in Stage
code when S0ix is enabled and so we should hide these in the
ConfigEditor if S0ix is enabled.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
There is a discrepancy between how Linux reads GPIO
and how bootloader is presenting it. This causes Linux
distros to crash, even in the installer,unless a kernel
module parameter has been passed:
'module_blacklist=pinctrl_elkhartlake'
The customer, Red Hat, is using RHEL 8 4.18.0-315.
There appears to be a discrepancy between how Linux reads GPIO and how
the Intel BIOS is presenting it.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This patch fixes TSeg region full problem after multiple
warn reset. Each time of warm reset, except S3 resume, the
TSeg region should be clear.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
For EHL, PCH & PSE TSNs are required to be turned on for ethernet
connection. However, TSN configurations binaries (TSN Mac address,
TSN manual config & PSE TSN IP config binaries) are optional, and
only used for refined controls.
This CL decouples optional TSN binaries loading and can be enabled
with BoardConfig flag "ENABLE_TSN". If those binaries are
not included, OS TSN driver will load TSNs with default configs and
assign MAC address to them dynamically.
ENABLE_TSN is turned off by default.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
EHL stitchifwi script enables user to replace IFWI IPFW components
during stitching time.
This CL enables user to only replace IPFW component only if the
specific component is included in IPFW folder of stitch workspace
directory.
Besides, this CL also adds TCC CRL to the replaceable IFWI IPFW
components list.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Here are the changes:
1. Update mismatched & incorrect config options & variables
2. Fix invalid boot options configs
3. [common] Include 'preOS + mender' support for boot flags in
boot options template
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Allow user to include TCC CRL binary to be included in SBL
binary build. The script will check if crl.bin is there (binary
folder) and then only include it.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
TSN GBE PMECTRLSTATUS register returned 0x3 after
booting into OS and only occured in Fusa sku
This fix will check TSN PMECTRLSTATUS register and
update value to 0x0 if non-zero value was returned
Only applicable if TSN is enabled
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
To support rtcm image for all boot options in SBL EHL
Uncomment boot flags and image type in Tcc_Feature.dlt for
enabling tcc in dedicated boot option
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Enable DAM option in stitchifwi script for
ITP/CCA debug purpose with -o debug paramter
Example: To enable SATA and DAM enabled "-o sata;debug"
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Update EHL BoardPkg version to 2.0 to allign with current
software package version:
PROJ_MAJOR_VER -> 2 (Maintenance Release candidate)
PROJ_MINOR_VER -> 0 (1st revision of MR1 release)
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Re-enable sbl_rtcm in EHL boot option due to
mistakenly removed it in previous commit of
f01a5b33fb
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Enable POSC for all boot medium in Cfgdata_BootOption.yaml
by default
If Non-Fusa sku was detect and the boot flag will
change to exclude POSC
User can modify the boot flag to exclude the POSC in
yaml file as well
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Add latest Intel® Time Coordinated Computing support for EHL.
Here are the changes:
- Update the TCC subregion layout
- Use the common TCC config data
- Use the common TCC library for RTCT table
- Support TCC DSO cfg, Cache cfg and CRL binaries loading
- Rename TCC variable to follow TCC V2 naming
- Increase the stage 2 size from 0x89000 to 0x91000 to accommodate
the new changes
- Add latest FspmUpd and FspsUpd header files for TCC v2 support
(will be removed once FSP github updated the latest EHL FSP package)
- Change default boot options for RTCM support
TCC mode is turned off by default.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
Fix mPchSciSupported flag checking before changing the
flag value of boot option.
This bug was introduced from commit
b78cbcf128
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Aiman Rosli