This patch added a new 64bit base field in the loader serial
port hob to support 64bit resource. The revision is updated
to 2. It is backward compatible with revision 1.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PatchChecker.py still complains lots of files with
trailing whitespace and tabs. This patch addressed these
error reporting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
In order to improve the UEFI payload display performance, it is
desirable to have the framebuffer as write-combining for cache
attribute. This patch added a common API to enable this and it
enabled the GFX framebuffer cache for QEMU and TGL. Other
platforms still need porting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since the commit below was reverted
24f5aa59b5. The cache flush
need to be moved into the place where data consistency
across warm reset is required. The patch added the WBINVD
to flush the cache before "fwupdate" command issues warm
reset.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
For non UEFI payload, SBL will install dummy SMI handler for
security concern. For UEFI payload, SMM rebasing is expected
to be done itself. This patch enabled this feature for APL and
CFL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In normal UEFI payload case, the UEFI will handle SMM rebasing.
If SMM rebasing is handled by SBL, SBL will put a dummy SMI handler
at the new SMBASE to prevent SMM hang. Beyond SMM rebasing, it
is also required to program SMRR registers. This patch added this
support for core code. It also added TSEG PCD init for CFL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL release debug output has more than what is expected.
This patch reset some of the debug message to proper level to limit
debug message for release build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch configured UP2 GPIO213 default to be output with level
high. It will select the PCIe interface as default. The original
default was mSATA.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current APL SBL code will enable IA_UNTRUSTED mode only at end of
firmware notification. It might be too late for certain conditions.
This patch moves it to be set at end of stage in SBL. In this way,
it ensures the bit is set before launching any external payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixes the multiple build issues which are observed
when ENABLE_SOURCE_DEBUG config is set to 1.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
Linux reported incorrect MTRR mask programming in SBL. This patch
fixed this issue by using the proper MTRR mask for GFX FB.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL support to load PreOS and normal OS in a single boot option.
This patch tries to standardize the PreOS support.
The PreOS could be TrustyOS, PreOsChecker or others.
As long as PreOS flag is set in boot option, SBL will load and
boot PreOS before normal OS. If the preOS has specific requirement,
it could be addressed using PreOS image type.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Python 3.4 and above have deprecated imp module in favor of
importlib. This patch removed imp module usage from SBL, and
used importlib instead.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed link error for APL NOOPT build due to compiler
intrinsics functions. However, due to APL hardware requirements,
it is not feasible to fit NOOPT build into real flash. This
patch will not fix the NOOPT build error caused by code size issue.
For example, the following error might still occur for APL NOOPT
build:
Invalid the required fv image size 0xe3b0 exceeds the set fv image
size 0x6000
The APL SOC requires Stage1A to fit into 32KB. Since FSP-T will take
8KB, it only gives 24KB for SBL Stage1A code. NOOPT build will create
about 56KB for Stage1A, and it is impossible to fit into the layout.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The structure of ME_BIOS_PAYLOAD varies on silicons. So, it's moved to
silicon directory and common structures are in MeBiosPayloadDataCommon.h.
- MeBiosPayloadDataCommon.h in CommonSocPkg
- MeBiosPayloadData.h in the specific silicon package
Additionally, DEBUG_VERBOSE message level is used for HeciCore.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This allows APL target to use the common HECI library.
The APL target uses the common HeciLib from CommonSocPkg,
and overrides MeChipsetLib for Apollake specific APIs.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch did the following
1) Added common routines LocateVbtByImageId to look for VBT image using
ImageId provided by configuration data and GetVbtAddress.
2) GetVbtAddress routine will provide abstaction for all platforms
irrespective of multiple VBT or single VBT used by the platform.
3) LocateVbtByImageId routine is moved from platform local function to
common package.
4) VbtImageId configuration option defined in QEMU platform config is
moved to common configuration in CfgData_Common.yaml
5) ApolloLake VBT ID selection is now done using configuration data.
6) Added latest VBT binary for CFL, WHL is using existing VBT.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current ConfigEditor relies on the original input data format in YAML
to determine how to represent data in GUI. For example, if the data
value is HEX in YAML, then the data will be displayed in HEX format.
This patch switched to use the specified format type to reformat the
value string so that the display is always consistent with the required
format type.
It fixed#844.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added support to launch payload module on top of OsLoader.
Comparing with payload binary, payload module will utilize the API
services provided by OsLoader, so it will have smaller size. Other
than this, the concept is exactly same as normal payload. For payload
module, additional parameter is required to pass into the payload
module entry point.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted some alignment on PCI resource allocation so
that PCI resource is more efficently utilized. It aslo adjusted
the framebuffer MTRR range to match PCI resource allocation.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enables OS to allocate 64bit PCI resource on APL platform.
It will help resolve some cases where 32bit PCI resource is very
limited.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The new YAML format represented some data structure a little bit
differently from original DSC format. This patch did minor adjustment
to make the build pass on APL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
As discussed in the RFC, SBL will use YAML format for CFGDATA format
going forward. This patch converted CFGDATA files from DSC format into
YAML format for QEMU, CFL and APL platforms.
To convert existing DSC file into YAML file, please use tool:
python BootloaderCorePkg\Tools\Dsc2Yaml.py <Path to CfgDataDef.dsc>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed some ACPI issue on APL platform. When VT-d is
disabled, DMAR table should not be populated in ACPI. This patch
fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
KEY IDs are extended to include key type and sizes.
Platforms can configure corresponding RSA2048 and
RSA3072 KEY IDs. Updated tools to adjust hash type
based on key size.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch enables usage of key id for private keys
in slimboot repo. Key ids are configured in
BuildLoader and platform BoardConfig files.
SLIMBOOT_KEY_DIR is set to default folder outside
sblopen.
Generation of extrenal Keyhash OS key hash to be configured
for QEMU/CGL/APL with appropriate keys.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
The unnecessary wbinvd() is removed from the common ResetSystemLib,
and it moves to a platform specific reset routine.
Signed-off-by: Aiden Park <aiden.park@intel.com>
- Created BaseIpcLib
- Sideband Interface picked from
tianocore/edk2-platforms
branch: devel-IntelAtomProcessorE3900
commit: 181f9e6c6ccde6e3fa62278b3a8b39cfb5844a7c
- IPC Interface picked from
tianocore/edk2-platforms
branch: devel-IntelAtomProcessorE3900
commit: 181f9e6c6ccde6e3fa62278b3a8b39cfb5844a7c
- Updated Stage1BBoardInitLib.C with a test function
Signed-off-by: Andrey Vinokurtsev <avinok@gmail.com>
This patch fixed OsLoader boot from SD card issue on Intel APL CRB
borads. The SD/eMMC library was updated to follow the proper sequence
for SD card. Also platform code was updated to detect SD card and
apply SD card power using proper GPIO pins.
It fixed#729.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current APL StitchIfwi.py does not enable PDR region due to incorrect
XML option. This patch fixed this and also adjusted the default PDR
region to be 4KB to save space.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
PcdVerifiedBootHashMask is no longer used while
verification except for stage1B. Remove Hash mask and
added PcdVerifiedBootStage1B for stage1B verification.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
For APL StitchIfwi.py script, if relative path is provided for the
stitching workspace, the stitching process will error out. This
patch fixed this issue by converting the relative path to absolute
path before passing it into the stitching functions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted the memory SKU ID detection for UP2. There is
another GPIO PIN which needs to read to get a full memory SKU ID.
This has not been only tested on SKU 0 so far due ot lack of other
SKU UP2 boards.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added UP2 specific VBT table to enable both HDMI an DP
ports. The VBT from FSP repo can only support HDMI.
It fixed#651.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled APL X64 boot. In X64 mode, more heap is required
for Stage1A since it needs to build page tables. As part of it, APL
CAR region map has been re-arranged so as to save more space. This
has been tested on LeafHill CRB board.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current build only allows board to customize the DSC libraries.
It is better to allow more flexible DSC customization. This patch
enabled this capability. Board can override library, PCDs, etc.
As part of it, the old GetDscLibrary() interface will be deprecated.
Please use GetPlatformDsc() instead.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Add missing X64 MdePkg Library
This adds some missing Library from EDKII Stable201911.
- MdePkg/Library/BaseMemoryLibRepStr/X64
- MdePkg/Library/BaseSynchronizationLib/X64
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Make X64 target buildable
This is just to build X64 target - Not functional.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added UP2 board memory SKU3 support. This was enabled
by trying different memory configurations to find the working
configurations. It might not be optimal, but a good start point.
Special acknowlegement to andreyv1978 who did the enabling on his
board and contributed the code back.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Add SMI status register
Add SMI lock register
Add REG_TYPE_MMIO register type
Zero SMM HOB
Fill SMI lock info for CFL and APL platform
Signed-off-by: Guo Dong <guo.dong@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Maurice Ma