The WHL(and CFL-R) has its own SpiFlashLib, but it's almost identical
to common SpiFlashLib except of silicon specific part.
Therefore, CoffeelakePkg will have its own PchSpiLib and re-use common
SpiFlashLib.
- Remove CoffeelakePkg SpiFlashLib and related files
- Use commmon SpiFlashLib
- Use CoffeelakePkg SpiFlashLib
Signed-off-by: Aiden Park <aiden.park@intel.com>
QEMU has its own SpiFlashLib and SpiFlashLib.h file.
But, the header file is identical to the one in Silicon/CommonSocPkg.
Therefore, remove QEMU's one and re-use the common header file from
Silicon/CommonSocPkg.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Use common SpiFlashLib and PchSpiLib of Silicon/CommonSocPkg.
- No more use of SpiFlashLib from BootloaderCommonPkg
Signed-off-by: Aiden Park <aiden.park@intel.com>
Platform Device structure PLT_DEVICE supports both PCI and MMIO formats.
But, SpiConstructor gets SPI device info from Platform Device Table
and it always assumes the info as a PCI format. This patch is to support
both formats.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Remove Silicon specific part from SpiFlashLib and use separate
PchSpiLib for Silicon specific part
- Remove Silicon specific code from SpiFlashLib
- Use PchSpiLib for Silicon specific part
- Remove unnecessary ScSpiCommon.h file
Signed-off-by: Aiden Park <aiden.park@intel.com>
Most of PCH SPI controller are using same mechanism to access SPI BAR
and to control BiosWriteProtect by using SPI PCI device/function.
But, a certain Silicon may use different way to access them.
ex) SPI BAR from LPC A reg, BiosWriteProtect from LPC B reg
Split SpiFlashLib into two parts.
- SpiFlashLib for common part
- PchSpiLib for silicon dependent part
This patch is to prepare the split.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This is prerequisite step to clean-up SpiFlashLib.
- Copy from BootloaderCommonPkg to Silicon/CommonSocPkg.
No code change at all.
- Keep the existing BootloaderCommonPkg SpiFlashLib.
To avoid build failure on existing boards.
The existing boards will use new one at the final clean-up stage.
Signed-off-by: Aiden Park <aiden.park@intel.com>
On WHL after booting to Windows, SCI interrupt storm was seen due
to GPE event 111 (2-tier GPE event). This event needs to be handled
when RTD3 table is implemented. However, current code has _L6F
ASL code without RTD3 table. This causes the SCI event to be enabled
in Windows. Since there is no real handler to clear the SCI event,
SCI interrupt storm will occur. This patch commented out the _L6F ASL
method.
Tested this on WHL. The CPU utilization drop down from original 10%
to close to 0% for system interrupts.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There is an issue in current SBL Stage2 code to check if the UEFI
payload is built from open source. It was done by checking the
1st DWORD using Dst[0]. However, during the FV loading, the value
at Dst[0] might have been changed since LoadFvImage() can move the
FV to a new location. This patch cached Dst[0] before calling
LoadFvImage() so that it can always get the oringal value.
It fixed#343.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Container type can be input from command line
from a list of [NORMAL, CLASSIC, MULTIBOOT] while
generating a container using GenContainer.py.
Setting default as NORMAL.
Revert varnames of out dir and key dir for commands
other than create container, as this is breaking stitch.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Add support to load the boot image from container.
Container must be signed using the same private key
as the key used to sign IAS (i.e. IAS_PRIVATE_KEY).
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current logic enables all EN bits in PMI_EN in order
to clear single PWRBTN_EN bit. This should not happen.
Corrected the logic so that only PWRBTN_EN is cleared and
the other EN bits are untouched.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
If FPDT->Length is just the size of FIRMWARE_PERFORMANCE_TABLE,
BOOT_PERFORMANCE_TABLE and S3_PERFORMANCE_TABLE are overwritten
by the next Table in ACPI init. Therefore, make the size in the
header as sizeof(INTERNAL_FIRMWARE_PERFORMANCE_TABLE) so that
the next table starts after INTERNAL_FIRMWARE_PERFORMANCE_TABLE.
Otherwise, S3 Perf Table can't be located on S3 resume path.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
On UP Xtreme board current code only supports PCH UART debug port.
But this board has two extra UART ports behind SIO chip F81801.
This patch added required initialization for the SIO chip to enable
UART on SIO. It can be enabled through platform data during stitching.
For exmaple,
"-p 0xAA000210" parameter in stitching will select PCH UART2.
"-p 0xAA00FF10" parameter will select SIO COM1 as debug device.
"-p 0xAA00FE10" parameter will select SIO COM2 as debug device.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
GenContainer.py tool can be used to create a container
with the boot files as follows:
python %SBL_ROOT%\BootloaderCorePkg\Tools\GenContainer.py create
-cl CMDL:<cmdline.txt> KRNL:<vmlinuz> INRD:<initrd>
-o <Out> -k <Key>
<cmdline.txt> = command line file
<vmlinuz> = kernel image
<initrd> = initrd image
<Out> = dir/file where final Pods Image is copied
<Key> = Private signing key file/dir path
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch formats the CFGDATA value string into a standard format
for the generated DLT file. It will format the array string using
its structure type including UINT8/16/32/64.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added support to load CfgData DLT file through
ConfigEditor command line interface. It makes it easy to
run ConfigEditor. It requires DLT file to be in the same
folder as the CfgDataDef.dsc file.
EX: python ConfigEditor.py Brd1.dlt
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current ConfigEditor only supports UINT8 format cell in table.
This patch added support for variable cell width including UINT8,
UINT16, UINT32 in table widget. Test configuration items were
also added in QEMU to test these format.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Slim Bootloader code has both CRLF and LF line-ending files.
Before cleaning-up, disable force_crlf for now.
Change-Id: I2e73ccfb8814ea8638c078f284ca7dbeca298e8b
Signed-off-by: Aiden Park <aiden.park@intel.com>
The PatchCheck.py does basic rule check on commit message and code.
This can be used as one of pre-commit checker before doing PR.
ex) N: the number of commits from HEAD
python BaseTools/Scripts/PatchChecker.py -N
Change-Id: Ib75aafa2c3eb3408de08f7fab7fff4934715547c
Signed-off-by: Aiden Park <aiden.park@intel.com>
- 'OpenFile may be used uninitialized' in ExtLib
- 'undefined reference to memcpy' in FatLib
- 'Lasa/Laml may be used uninitialized' in TpmLib
- 'Adjust may be used uninitialized' in Stage2Support
Signed-off-by: Aiden Park <aiden.park@intel.com>
Compile optimization sometimes needs to be disabled for debugging.
EDKII BaseTools provide NOOPT target, so leverage it.
The default GCC '-O0' and VS '/Od' option results in huge size image,
so the optimization level is adjusted with approximately level.
Add a new build option '-no' or '--noopt' for NOOPT target
- Release build option '-r' will ignore '--noopt' option
ex) python BuildLoader.py build qemu --noopt
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current IfwiUtility does not support the old non-redundant image
layout format. This patch added support for non-redundant image by
defining a new FLASH_MAP_REGION key.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When config data define with size bigger than 1 byte in array,
GenCfgData will parse as zero value.
This patch to fix the issue.
Signed-off-by: Teo, Boon Tiong <boon.tiong.teo@intel.com>
Add GetNextAvailableComponent() and authenticate the
components after registering them in CONTAINER_LIST.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch sets the default PEIM rule to use TE image format.
In this way it does not need rule overriding anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
To assist source level debug, it is better to always load PE/TE images
at page aligned memory address so that the script can locate the image
much easier. This patch changed the AllocatePool to AllocatePages for
component loading inside a container.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
QEMU compiling will fail when EXECUTE_IN_PLACE is set to 1 due to
size issue. Even after fixing size issue, the execution will still
fail. It is because the variable services will try to put SPI into
command mode while code fetching will fail if it is executed from flash.
This patch added necessary code to skip variable tests in Stage1B and
Stage2 when XIP is enabled. It fixed#324.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch provides the basic infrastructure to add a
Debug Port Table 2 (DBG2) to specify one or more ports
for debugging purposes. More info reg DBG2 @ :
https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn639131(v=vs.85)?redirectedfrom=MSDN
If the platform wants to report a debug port to Windows,
it should patch the DBG2 template provided with the
corresponding debug port information. And this updated
DBG2 must be referenced in RSDT.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch will change the code to always use absolute path
for stitching zip file, if relative path is provide, code will
convert it to absolute path.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current code will try to append a NULL char at the end of the
config file buffer to ensure the string is terminated properly.
However, it did that without considering the buffer size. The
current config buffer could have been fully used and no more
space is available to append an extra NULL char. If this happens,
during the pool de-allocation, the assertion will be seen due to
buffer overflow. This patch increased the config buffer size by 1
to ensure it will have space to append string terminator.
It fixed#319.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to make ACRN to boot, it is required to set boot from eMMC
RAW partition 1. However, current boot option is set to 0, which
caused the boot failure. This patch updated the SwPart to 1 and filled
the LBA with expected format. It fixed#317.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current Gpio config provides a way to select PadMode. But
Native Functions for a PCH are just numbered #1,2, etc. and
do not provide enough information for the end user while
configuring the PadMode.
This patch adds the required Native Function information help
strings in the drop down menu while configuring the PadMode.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Error: conversion from 'UINT32' to 'UINT8', possible loss of data
MADT ProcessorId and ApicId has the size of UINT8. Cast the size from UINT32 to UINT8.
Change-Id: I3f46b2015b0d21c2b3e2f9389ecb8d5364ed5a5e
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will detect CPUs up-to 255 and update MADT ProcessorLocalApic entries
with the detected CPU information.
- Set PcdCpuMaxLogicalProcessorNumber to 255 in QEMU BoardConfig.py
Test>
qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio
-pflash Outputs/qemu/SlimBootloader.bin
-smp 8
Signed-off-by: Aiden Park <aiden.park@intel.com>
Make PcdCpuMaxLogicalProcessorNumber configurable on a Board
- PcdCpuMaxLogicalProcessorNumber = 16 by default
- Configurable by CPU_MAX_LOGICAL_PROCESSOR_NUMBER in BoardConfig.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
Currently, the common hook UpdateMadt() was updating fixed size of
ProcessorLocalApic entries.
This allows the hook to append ProcessorLocalApic entries with the number
of detected CPUs in runtime.
Signed-off-by: Aiden Park <aiden.park@intel.com>
To make PlatformUpdateAcpiTable() hook its contents and length easily,
allocate a memory from low to high and appends each tables to higher direction
Signed-off-by: Aiden Park <aiden.park@intel.com>
- Add BistVal in STAGE1A_ASM_HOB structure
- Use MM0 register to preserve the BIST value
- Push BistVal while setup HOB in stack
- Add check for CPU BIST failure and halt the system when failed
Signed-off-by: Himanshu Sahdev aka CunningLearner sahdev.himan@gmail.com
This patch added support for CFLS and CFLH stitching by patching
proper xml file for the platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Currently in Stage1B it defined gpio table for pre-memory, but no one
program that gpio table. This patch adds it.
Move full GPIO table program from Stage1B to Stage2
Remove unused global variable mRsvdSmbusAddressTable in Stage1B.
TEST= Build success.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Aiden Park