Removed GopConfigLib and GopConfig header files
SBL will skip the runtime VBT update and will only consume updated VBT
SBL only pass the VBT reference to FSP without perform update
The updated VBTs for all platform boards will stored in VbtBin folder
Signed-off-by: Kobe <kok.tong.ong@intel.com>
If the function actually returns a null value,
a null pointer dereference will occur.
In InitializeSmbiosInfo: Return value of function which returns
null is dereferenced without checking (CWE-476)
Signed-off-by: Randy <randy.lin@intel.com>
Define of platformId is : [UINT8 : 5;]
Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
result_independent_of_operands: StitchData->PlatformId < 32
is always true regardless of the values of its operands.
This occurs as the logical second operand of "&&".
Signed-off-by: Randy <randy.lin@intel.com>
This patch adds ACPI DMAR table for CFL.
Some VT-d init code are ported from EDK2.
Test method:
1. dump acpi tables: acpidump -b
2. check the dmar table: iasl -d dmar.dat
Verify: CFL-s RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
CFL does not have Linux-native stitch tools.
This patch uses 'wine' as a wrapper to support stitching
SBL under Linux env.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
The steps of OEM key revocation are:
1. Replace OEM KM (signed with key2) by updating CSME
2. Replace BIOS region (signed with key2)
3. Reboot with new BIOS region (to make key1 inactive)
4. Revoke key1
Before this patch, it requires 2 firmware updates and 2 capsules for
step 1~2 and step 4 respectively. The patch combines them into a single
update/capsule.
To implement the feature, the patch:
1. Double max # of payloads to allow CSME/CSMD/BIOS/CMDI update
in one capsule image.
2. Prevent from failing update of a critical component.
e.g., if step 1(CSME) fails, step 2(BIOS) should be skipped
Verified cases:
Case 1: Capsule having CSMD/CSMD/BIOS/CMDI.
Expectation: successful
$ python BootloaderCorePkg/Tools/GenCapsuleFirmware.py \
-p CSME FWUpdate.bin \
-p CSMD CsmeUpdateDriver.efi \
-p BIOS new_BiosRegion.bin \
-p CMDI cmdi.txt \
...(skip)
Case 2: Capsule having CSME/BIOS/CMDI but no CSMD.
Expectation: no update
Case 3: Inject fault flow (no partition switch after first flash),
Capsule having CSME/CSMD/BIOS/CMDI.
Expectation: no CMDI update
Verification: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch can reduce the chance of setting SBL_SOURCE when the
SBL root directory is not named as "SblOpen" or when the scripts
are run from the path other than the SBL root directory. Also note
that os.path.abspath() returns the absolute path relative to the
current working directory instead of the real path of __file__.
So in StitchIfwi.py, sblopen_dir was incorrect since the working
directory had been changed before calling stitch().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This reverts commit 1caacefeb5.
The USB port that does not respond to USB bus enumeration is port 8 on
the newer UPX board. The old UPX board might have different behavior.
The original commit was valid on old UPX board only, and this patch
reverted it. Confirmed the USB error message disappeared on the new
UPX board after the reverting.
Signed-off-by: Maurice Ma <mauricemx.ma@gmail.com>
This patch added a new 64bit base field in the loader serial
port hob to support 64bit resource. The revision is updated
to 2. It is backward compatible with revision 1.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Pass in a pch_series param to GpioDataConvert tool
to fetch the correct gpio group info for a platform
based on the pch series.
The tool expects the platform specific config file to
implement a function vir_to_phy_grp () that returns
a BOOL value based on:
If vir_to_phy_grp = False, SBL's config has A->0, B->1 etc. mapping.
And GpioSiLib.c or GpioInitLib.c corresponding libraries will map
this virtual group #s to real physical group #s (if not same).
If vir_to_phy_grp = True, SBL's config has A->G1, B->G2 etc.
physical mapping directly, so the GpioLib library uses this as is.
GpioDataConfig.py file was added for ADL platform.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Current TGL platform set 0 as the PCI end bus number in ACPI
MCFG table. And it caused incorrect MMCONFIG range calculation in
Linux. This patch updated the template to use 0xFF as the PCI
end bus number.
It should fix#1481, to be confirmed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When run as part of an automated system it's important to ensure that
any failure is reported to the calling process. Writing an error message
and then exiting indicating success leads to difficult-to-diagnose
problems.
Signed-off-by: Mike Crowe <mac@mcrowe.com>
On CFL and CML, the board hook PostMemoryInit was called before
FspMemoryInit API. This should be called afterwards instead.
This patch fixed this issue. It is because of missing "break"
statement. It fixed#1435.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
Current GpioLib uses 2 bits from OtherSettings to
configure RxRaw field in GPIO PAD CFG DWORD 0. But
Gpio config templates are missing the option to configure
this feature. This patch adds the option in template.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since the commit below was reverted
24f5aa59b5. The cache flush
need to be moved into the place where data consistency
across warm reset is required. The patch added the WBINVD
to flush the cache before "fwupdate" command issues warm
reset.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On UPX, one USB2 port does not respond properly during PCI enumeration.
It needs to be disabled. The current SBL code disabled the wrong port.
It should be port 10 (USB2 index 9).
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
During UP Extreme board enabling, trace hub interface was enabled
to help debug. But it should be disabled by default. This patch
fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Seems some recent patches may have added additional
size to OS Loader and now the internal pre-commit build
test in Jenkins is failing due to not enough space
for PAYLOAD. Other platforms are also using 29000h
so might be best to increase the CFL value as well.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This patch fixes TSeg region full problem after multiple
warn reset. Each time of warm reset, except S3 resume, the
TSeg region should be clear.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Default Bpmgen params created by bpmgen tool
has unicode characters. This patch fixes reading the
file with unicode chars.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch provides exampole on how to enable mailbox debug port on
WHL. To enable it, the following needs to be set in BoardConfig.py.
self.DEBUG_OUTPUT_DEVICE_MASK = 0x07
self.CONSOLE_IN_DEVICE_MASK = 0x00000005
self.CONSOLE_OUT_DEVICE_MASK = 0x00000005
Also adjust the PcdMailboxDebugPortMmioBase value in BoardConfig.py
as needed.
On host side, python script can be used in ISD to read/write this
register using IPC interfaces. EX:
import ipccli
ipc = ipccli.baseaccess()
ipc.stateport.cnp_tpsb0.tap2iosfsb32 (...)
Please refere to MailboxDebugPort.py for example.
This was tested on UPX board with CCA debuger connected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows to use a mailbox register (DWORD) to support debug
port. If CCA debug is connected, it is possible to access certain
SOC register through BSSB. Then this register can be used for debug
console input/output.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Recent addition of '-op' argument may have
unintentionally created an issue by using an
unassigned variable 'work_dir' where the
intended variable to be used may have been
'stitch_dir'. This patch resolves the issue
and able to successfully stitch an IFWI once
again.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Use the newly added PchSbiAccessLib in common package,
for all the current platfroms. Platform specific PchSbi Lib
is removed.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Currently final IFWI gets generated output path.
Copy the signed slimboot binary to out path.
Added option for outpath.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch added required support to enable PCI 64 bit resource
allocation. By default, all downgrading is enabled so that it has
the same behavior as current code. To enable 64 bit resource,
set related downgrading flag to 0.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When S3 resume fails for some reason, the power button status will
be not be cleared on next boot. It might trigger shutdown event in
payload. This patch will clear power button status bit on normal
boot flow so that system can still boot properly.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For appending Save/Restore structs in TSEG area,
bootloader should reserve space for TotalSize and
for certain structs, only header info should be
actually populated. Rest should be all Zeros.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
For non UEFI payload, SBL will install dummy SMI handler for
security concern. For UEFI payload, SMM rebasing is expected
to be done itself. This patch enabled this feature for APL and
CFL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In normal UEFI payload case, the UEFI will handle SMM rebasing.
If SMM rebasing is handled by SBL, SBL will put a dummy SMI handler
at the new SMBASE to prevent SMM hang. Beyond SMM rebasing, it
is also required to program SMRR registers. This patch added this
support for core code. It also added TSEG PCD init for CFL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL release debug output has more than what is expected.
This patch reset some of the debug message to proper level to limit
debug message for release build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This Patch did the following
- TsegSize config options is defined in CfgData_Memory.yaml.
- with 64GB RAM, slow boot issue was reported on ubuntu_20.0.
Root cuase of the issue is due out of MTTR's and unable to cover
portion of higher memory ranges. this patch fixes this issue.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
This patches fixes the audio record issue using onboard 3mm jack.
TEST= booted to windows on both CFL-S & CFL-H board and verified
Audio playback and record is working using onboard 3mm jack.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
similar to CML, CFL also uses both IOB2 & IOB3 ports to pass the info
and generate an SMI. where as common code ACPI implementation uses
only IOB2, hence TPM2 ACPI tables are ported from CML platforms.
This patch fixes physical presence query and TPM clear issue on windows.
TEST: boot to windows on CFL-H platform and verified TPM physical
presence and TPM clear command is successfull.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
WHL CRB board is configured to boot different payload based on GPIO pin
status, which is not working currenly.
this patch ensures to boot to Osloader payload when PayloadSelGpioData=1
otherwise boot to UEFI payload.
TEST= Boot test on WHL CRB and verified board able to switch between
OSloader & UEFI payload based on DIP switch R4H1B_4 status.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
Python 3.4 and above have deprecated imp module in favor of
importlib. This patch removed imp module usage from SBL, and
used importlib instead.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
As per board design the DDI ports are routed as per below,
CFL-S:
DDI1-->PORTB-->LSPCON-->HDMI
DDI2-->PORTC-->DP
CFL-H:
DDI1-->PORTB-->DP1
DDI2-->PORTC-->DP2
DDI3-->PORTC-->LSPCON-->HDMI
Hence add separate VBT binaries accordingly.
-Set HPD of DDI port F to disable as default since it's not used by
H/S/U processor line.
TEST: verified onboard display's ports booting to UEFI shell & Yocto.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
Current CFL SBL build with DEBUG FSP will fail due to size issue.
This patch fixed this issue by adjusting size properly when DEBUG
FSP is used.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch addressed an issue while detecting the
BOM ID for Upx platform which is causing the MRC
to fail.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch expanded HECI service to include send, receive and
reset interface functions. This helps in making firmwareupdatelib.c
and PSDlib common across platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Kobe