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fix: [Common] Operands don't affect result for PlatformId (#1940) 

Define of platformId is : [UINT8 : 5;]

Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
result_independent_of_operands: StitchData->PlatformId < 32
is always true regardless of the values of its operands.
This occurs as the logical second operand of "&&".

Signed-off-by: Randy <randy.lin@intel.com>
This commit is contained in:
randylintw 2023-06-30 00:43:18 +08:00 committed by GitHub
parent 475ff9daca
commit 9dc4a2f7ad
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 8 additions and 24 deletions
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4
Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -115,9 +115,7 @@ EarlyPlatformDataCheck (
SetDebugPort (PcdGet8 (PcdDebugPortNumber));
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}

4
Platform/ApollolakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -55,9 +55,7 @@ EarlyPlatformDataCheck (
SetDebugPort ( PcdGet8 (PcdDebugPortNumber));
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}

4
Platform/CoffeelakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -163,9 +163,7 @@ EarlyPlatformDataCheck (
SetDebugPort ( PcdGet8 (PcdDebugPortNumber));
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}

4
Platform/CometlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -87,9 +87,7 @@ EarlyPlatformDataCheck (
SetDebugPort (0xFF);
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}

4
Platform/CometlakevBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -83,9 +83,7 @@ EarlyPlatformDataCheck (
SetDebugPort (0xFF);
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}

4
Platform/ElkhartlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -94,9 +94,7 @@ EarlyPlatformDataCheck (
SetDebugPort (PcdGet8 (PcdDebugPortNumber));
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}

4
Platform/IdavilleBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -59,9 +59,7 @@ EarlyPlatformDataCheck (
StitchData = (STITCH_DATA *)(UINTN)0xFFFFFFF4;
if (StitchData->Marker == 0xAA) {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
} else {
// Use the default port defined in BoardConfig.py
SetDebugPort ( PcdGet8 (PcdDebugPortNumber));

4
Platform/TigerlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
View File

@ -89,9 +89,7 @@ EarlyPlatformDataCheck (
SetDebugPort ( PcdGet8 (PcdDebugPortNumber));
} else {
SetDebugPort (StitchData->DebugUart);
if ((StitchData->PlatformId > 0) && (StitchData->PlatformId < 32)) {
SetPlatformId (StitchData->PlatformId);
}
SetPlatformId (StitchData->PlatformId);
}
}