Added Null template for FusaConfigLib. Platforms supporting FuSa should
follow this template for enabling FuSa configuration prior to FSP-M and
FSP-S.
Added ADL/RPL CfgData fields for FuSa according to SBL FuSa software
requirements, and dlt file for enabling FuSa and related configuration.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Add support for Up Xtreme i12 ADLP based board.
The PCIe M.2 slot CN12 on the board is able to detect NVMe SSD.
Debug output is enabled at header CN9 on the board(e.g. UART1)
Tested to boot with OS loader payload and UEFI payload.
To stitch the SlimBootloader.bin with IFWI uses StitchLoader.py script with '-p' as given below:
python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/adlp/SlimBootloader.bin -o sbl_upx12_ifwi.bin -p 0xAA000104
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
- Match the Pep constraints cfg with that of default.
- Sync few FSP cfg settings.
- Minor clean up.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
When PcdVtdEnabled or MemCfgData->VtdDisable were disabled,
Fspmcfg->VtdDisable was being left at default value.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When SioInit code configures the COM portsin stage 2, it might have settings conflict
with debug interface. Remove it from FSP config to resolve potential boot issue.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
* fix: [RPL-P] TCC/TSN not being enabled correctly on RPL-P.
TCC and TSN enabling code was being platform limited to exclude RPL-P.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* fix: [RPL-P] remove PCH checks prior to enabling TCC/TSN.
Enabling TCC/TSN should be dependent on the PCDs and config data, not PCH
SKU.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Setup FSPM stack base and size based on the car size and
SBL stack and heap size.
This change could avoid the boot issue caused by FSP stack
overflow.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Guo Dong <guo.dong@intel.com>
This fix should apply to ADL-P also. For now we will avoid using #if's here
and address any ADL-P issues that come up.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP UPD FuSa toggles will be set based on new config data fields where
applicable or to predefined values when called for by the FuSa spec.
This requires setting PcdFusaSupport at build time in case platform FSP
doesn't support FuSa.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
RPL-P and ADL-P RVPs are essentially identical except for BoardID FRU.
Both need to work with SBL with RPL-P Silicon. To avoid duplicating
config data, this change will treat both as the same board.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
PcdTccEnabled was declared as a FeaturePcd which evaluates to a code symbol
and can't be used in a #if. From the preprocessor perspective it is always
undefined. Changed this pcd to a FixedPcd instead.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Added new platform ID for RPLP DDR5 CRB (COM-HPC board). This board has
no EC or board ID FRU, but it is so far the only board in the ADL/RPL
family like this so it is used as a board identification criterion.
Added DdiConfig table as well.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Updated FSP-M and FSP-S parameters to match with BIOS
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Include TCC specific code inside TCC feature flag to avoid
build issues on unsupported platforms.
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Added UPD Ddr4OneDpc in DLT file and removed hard coded value.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
1. Update BoardID and PlatformID for CRB board
2. Direct return after read board id from smbus to avoid boardid clashing
3. Added ddi config for CRB board
4. Update FSPM UPD due to common value across all sku
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
- Enable Tcc code path for N series.
- Disable WDT lock UPD since its causing the WDT to expire
even when valid DSO is provided.
- Code clean-up.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Update FSP UPDs and VBT changes as part of the ADLP MR release.
TEST=Tested to boot to OS.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
The default FSP UPD value for Lp5BankMode doesn't work
for all the platforms. It would help override it using
SBL configuration data if it is exposed.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added changes required for ADLN FSP Sync and
also did the following
1) Added SA config for DDR5 CRB
2) Initialized VBT to enable 2 HDMI and a DP port
3) Moved FSPM config to delta file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added support for ADLN platform.
EC related ACPI changes need to be reinvestigated
as disabling ECAvailable NVS change might be
sufficient to disable EC support in ACPI.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch fixes the test case where when a bad dso is
provided, it will revert back to the default dso settings.
TEST= Ran the test case successfully on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch adds Platform and Silicon support for Alderlake
project. Currently, FSP and microcode are not publicly
available. So build will fail with errors. We will update
the project whenever they are available.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Syahirah Sabryna