BIOS version is NEX ADL-S IPU 2024.4 (5045_03) FSP
FSP version is 0C00D550
platform version is 1.7
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_80_906a3_00000434.pdb', 'm_11_b06e0_00000017.pdb']
Signed-off-by: samihahkasim <samihah.kasim@intel.com>
This patch adjusted MTRR settings during PostTempRamInit notification to cover full flash
code region if Boot Guard profile 0 is used or Fast Boot is enabled.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000123.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
- Update Common MeChipsetLib to account for ARLS Me Bus.
Now,the bus number comes from Platform code:
if ARLS bus = 0x80, else bus = 0x0
- Update Heci Pci read calls in HeciMeExtLib to account for
both ARLS and ARL U/H BDF differences.
- Delete ARL specific MeChipset header files as it now uses
common header files from Common Package.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
S0ix failed when NVME attached due to incorrect PCI device configuration
Ported RootPortDownStreamPmConfiguration and related Libraries
To fix incorrect PCIE ASPM and L1 Configuration
Implementation is silicon-dependent due to registers definition
This implementation is using the following ADL PCIE PM PATCH as reference
3bbfe44bec
Signed-off-by: kokweich <kok.wei.chan@intel.com>
- FSP version is NEX RPL-P MR2 (0C.01.DE.40)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.2
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Use MeChipsetLib from the Common Soc package and remove
Silicon specific as its redundant
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This commit has the following changes:
1. Incorporates the omitted PcdAdlLpSupport to ensure the proper GPIO groups
are loaded for ADL-N.
2. Corrects the ACPI definitions for ADL-N GPIO communities.
3. Aligns the _HID of the ADL-N GPIO Controller with the Linux kernel's
pinctrl driver.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
* Update FSP/UCODE/for MR5 release
- update FSP version to IoT ADL-N MR5 (0C028940)
- update Microcode version to 17
- update platform version to 1.5
Basic boot tested on ADL-N CRB.
Signed-off-by: Randy <randy.lin@intel.com>
When the fsp.git commit id is updated,
it will update all platform fsp versions without testing.
Also adjust the fd size in adln50 project to avoid build break.
Signed-off-by: Randy <randy.lin@intel.com>
- update FSP version to NEX ADL-PS IPU24.3/MR6 (0C.01.D5.50)
- update Microcode version to 433
- update VBT version to 253
- update platform version to 1.6
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This commit resolves the issue where the SMI handler was not being triggered
during S3 resume. The problem was due to the functions RestoreS3RegInfo and
TriggerPayloadSwSmi not being called.
In addition, the commit also:
1. unset the PME_B0_EN as UEFI Payload does not have its handler
2. remove the ClearSmbuStatus() because
- the HSTS.B_SMBUS_IO_SMBALERT_STS in SMBUS (B0:D31:F4) should be
handled and cleared by device driver or an appropriate SMI handler.
- the ClearSmi() will clear GPE0_STS_127_96.SMB_WAK_STS if it is set
3. unset (FSPS) PeiGraphicsPeimInit and GraphicsConfigPtr during S3 resume
4. narrow the var scope of mSmmBaseInfo and mS3SaveReg
5. add required bitfield declaration
Verified with:
1. UEFI Payload + Ubuntu on EHL CRB (release build)
2. OSLoader (release build)
when FEATURES_CFG_DATA.Features.S0ix = 0
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
GPIO pad enabled for SCI need not be in unlocked
state.Hence removing the condition check.
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
- FSP version is IoT RPL-P MR1 (0C.01.CC.20)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.1
- minor fixes for BoardConfigRplp.py and StitchIfwi.py
- allow TCC/TSN to be enabled by FuSa DLT file
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Fixing build issue due to automatic cast conversion warnings from 64-bit
unsigned integers to 32-bit unsigned integers
Signed-off-by: Ong Ee Lim <ee.lim.ong@intel.com>
Upstream remaining internal MTL code to SBL open source.
Remove TCC specific code in Stage2BoardInitLib as feature is not supported
Signed-off-by: kokweich <kok.wei.chan@intel.com>
* [ADLP] Update FSP/UCODE/VBT for MR6 release
- update FSP version to IoT ADL-P MR6 (0C.01.CD.20)
- update Microcode version to 433
- update VBT version to 253
- update platform version to 1.6
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
* [ADLS] Update FSP/UCODE for MR7 release
- update FSP version to IoT ADL-S MR7 (0C.00.CE.20)
- update Microcode version to 34
- update platform version to 1.7
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
---------
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
* feat: [RPL-P] Upstream RPL-P code.
Upstream internal RPL-P code to Sbl open source.
FspsUpdUpdateLib updated for compatibility with both RPL-P and RPL-S.
RPL-P specific TCC code will be removed with TCC binary removal after
baseline is upstreamed.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* fix: [RPL-P] Addressing code cleanup review comments.
Function header comments and parameters cleaned up in FusaConfigLib.
FSP commit updated to latest, vbt removed in favor of local file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPL-P] Removed TCC Subregion support.
Current TCC feature design removes use of TCC subregions.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPL-P] Moved ucode and FSP to Silicon dir, removed PLT_SOURCE, added VBTs
FSP and microcode moved to Silicon folder to be in line with other
platforms. Removed references to PLT_SOURCE env variable. Added VBTs
and removed them from .gitignore.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
---------
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The patch installs reset handlers for FSP requested reboot.
The implementation of ResetShutdown and ResetPlatformSpecific
are different from the common lib (i.e., BootloaderCommonPkg/ \
Library/ResetSystemLib), so it results in a platform-specific
implementation.
Verified with Issue #2118.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
1) Added WA in pep.asl to put blocking NVME RP into standby/wakeup
2) Added PcdMTLPSSupport to support platform specific register value
Signed-off-by: kokweich <kok.wei.chan@intel.com>
added support for server platfrom which do not have ME
to skip the ME FW status check by comparing HeciBaseAddress.
Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
Biswas Arghya