Removed the source code related to TCC tools
including DSO switch, SWSRAM switch, TCC subregions
TCC Error Log switch, RTCM, RTCT
The code change applies on TGL/EHL/ADL/RPL/MTL
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
The PLATFORM_{NAME} macro is dynamically defined by BuildUtility.py, which
is based on the board file name. Since ASL has been merged into ADL-N, the
PLATFORM_ASL macro has become obsolete and is no longer valid. This commit
removes all instances of the deprecated PLATFORM_ASL.
Additionally, this commit addresses an issue where PLATFORM_ADLN was not
defined in Stage1ABoardInitLib.c during the build process for ADL-N. The cause
was that ConfigDataStruct.h was not included.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000123.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
Cause by cefbf78dae.
The default build will include the DACM region and the replace file should be present during stitch step.
Add fusa stitch option for users who want to replace that component in the BIOS.
Signed-off-by: Randy <randy.lin@intel.com>
- FSP version is NEX RPL-P MR2 (0C.01.DE.40)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.2
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Add support for Up Xtreme i12 RPL-P based board.
The PCIe M.2 slot CN11 on the board is able to detect NVMe SSD.
Debug output is enabled at header CN9 on the board(e.g. UART1)
Tested to boot with OS loader payload and UEFI payload.
To stitch the SlimBootloader.bin with IFWI uses StitchLoader.py script with '-p' as given below:
python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/rplp/SlimBootloader.bin -o sbl_upx12rp_ifwi.bin -p 0xAA000114
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
The patch improves the dev experience for configuring FSP-M UPDs:
RsvdSmbusAddressTablePtr and PchNumRsvdSmbusAddresses: Prior to this patch,
developers had to apply a memory patch at address 0xfffc3ff8, which was
cumbersome and inconvenient. With the introduction of this patch, developers
can now directly modify the DLT, simplifying the configuration steps and
improving workflow efficiency.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Python imp module is removed in 3.12+ and will cause a build error.
Replace with importlib.machinery.SourceFileLoader.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This commit fixes two AHCI operations:
1. AhciWriteBlocks: caused by wrong command
2. AhciGetMediaInfo: caused by wrong offset
The patches also updates the EFI_ATA_IDENTIFY_DATA to align with the ATA8-ACS.
In addition, this commit ports the following changes from EDK2, to enhance the
command completion and trace:
1. cc28ab7a1d7: MdeModulePkg/AtaAtapiPassThru: Check IS to check for command completion
2. b465a811006: MdeModulePkg/AtaAtapiPassThru: Add SATA error recovery flow
3. 64e25d4b062: MdeModulePkg/AtaAtapiPassThru: Restart failed packets
4. 91d95113d07: MdeModulePkg/AtaAtapiPassThru: Trace ATA packets
5. 4c7ce0d285b: MdeModulePkg AtaAtapiPassThru: Skip the potential NULL pointer access
Last, the commit adjusts OS_LOADER_FD_SIZE for several platforms for x64 build
Verified: Using BlockIoTest to test with SATA SSD disk on TGL-UP3
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- FSP version is IoT RPL-P MR1 (0C.01.CC.20)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.1
- minor fixes for BoardConfigRplp.py and StitchIfwi.py
- allow TCC/TSN to be enabled by FuSa DLT file
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
* feat: [RPL-P] Upstream RPL-P code.
Upstream internal RPL-P code to Sbl open source.
FspsUpdUpdateLib updated for compatibility with both RPL-P and RPL-S.
RPL-P specific TCC code will be removed with TCC binary removal after
baseline is upstreamed.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* fix: [RPL-P] Addressing code cleanup review comments.
Function header comments and parameters cleaned up in FusaConfigLib.
FSP commit updated to latest, vbt removed in favor of local file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPL-P] Removed TCC Subregion support.
Current TCC feature design removes use of TCC subregions.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPL-P] Moved ucode and FSP to Silicon dir, removed PLT_SOURCE, added VBTs
FSP and microcode moved to Silicon folder to be in line with other
platforms. Removed references to PLT_SOURCE env variable. Added VBTs
and removed them from .gitignore.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
---------
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Increase the size of the UEFI payload container to accommodate increased
payload size from Edk2 network driver and UNDI driver.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPLS] Update RPLS to align with MR1 release
Instead of sharing config data, RPL-S used full config data
from RaptorlakeBoardPkg. With this change, it updated its
default boot option (removed TCC binary) without impacting
other platforms. And in its default config data, it doesn't
need include SPD data for other platforms.
Will update FSP and Microcode separately once they are available.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* [RPLS] Update to use MR1 FSP
Update SBL to use MR1 FSP
Signed-off-by: Guo Dong <guo.dong@intel.com>
---------
Signed-off-by: Guo Dong <guo.dong@intel.com>
ADL groups GPIO pins into different sets for different PCH series.
The current CfgData uses ADLS's GPIO group sets as the base, and
overwrites the GrpIdx fields via DLT files for other PCH series.
This results in two issues:
1. "CfgDataTool.py export" command failed to extract DLT files
from SBL image, since it cannot identify the proper group
index in CfgDataExt.bin from the base table in CfgDataInt.bin
2. When using ConfigEditor.py to configure the PadGroup field of
GPIO Payload Selection, it will map to a wrong group index.
This patch separates CfgDataDef.yaml for each of PCH series
- add _CFGDATA_DEF_FILE in BoardConfig.py
- add board extension yaml files for Adln, Adlp, Adls
* CfgDataDef*.yaml
* CfgData_Gpio_*.yaml
* CfgData_PayloadSelection_*.yaml
- assign an invalid/unique GrpIdx for the unused GPIO group
* e.g. 1F, 1E, ..
- adjust GrpIdx of CfgDataExt_Upx12.dlt based on Adlp
- revise the payload selection information in DLT files
This patch also fixes the issue:
- When ConfigEditor opens CfgDataDef.yaml more than once, the
config changes will not be caught by "Save Config Changes to
Delta File"
It is because the "info" argument of build_cfg_list() in
GenCfgData.py will retain its value in the lifetime of
ConfigEditor, and the offset will overflow. So need to reset
the offset for a fresh load_yaml().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Removed GopConfigLib and GopConfig header files
SBL will skip the runtime VBT update and will only consume updated VBT
SBL only pass the VBT reference to FSP without perform update
The updated VBTs for all platform boards will stored in VbtBin folder
Signed-off-by: Kobe <kok.tong.ong@intel.com>
Vincent Chen