Commit Graph

549 Commits

Author SHA1 Message Date
Pastorcici, Mariano-paulX c50658ae6b feat: [common] Enable PCIe resizable BAR support
This commit adds support for PCIe resizable BARsupport.
The feature can be enabled by setting PcdResizableBarSupport
for the board build script and its disabled by default.

Signed-off-by: pastorcx <mariano-paulx.pastorcici@intel.com>
2024-09-09 10:30:57 -07:00
bejeanmo e3dfb721bb
fix: GenContainer.py not setting default auth type correctly (#2250)
When no auth parameter is specified on the command line, gen_layout
chooses auth type based on provided key, but this does not get correctly
applied to the monolithic signing component because of an order of
operations issue.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-08-15 13:02:37 -04:00
bejeanmo 203e62ef95
fix: Reload segment selectors after GDT Load in Stage1a (#2224)
If ResetVector GDT is different from that loaded in Stage1A SecStartup()
then segment selectors need to be reloaded after GDT is updated.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-07-10 15:47:51 -04:00
Bejean Mosher 04132381bd feat: Add BoardConfig field to control Stage1B remap
Adding new Board Config item REMAP_STAGE1B to control remapping Stage1B
into permanent memory after FSP-M. Decouple this from ENABLE_FAST_BOOT
and STAGE1B_XIP. This makes it simpler to enable this remap when the
slight performance boost may be needed, and leave it disabled by default.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-06-04 13:07:16 -07:00
bejeanmo 6a1da85c9f
fix: FSP 2.4 issues (#2171)
1) Some FSP 2.4 implementations are non-conforming and use FSPM_ARCH_UPD
instead of FSPM_ARCH2_UPD as indicated by the specification. Logic is
changed to check FSPM UPD header revision for structure version instead
of FSP spec revision.

2) MultiPhase FSP PhaseIndex is one-based so loop comparisons need to take
this into account. Side effect is that the last phase may be missed. No
current platform FSP is utilizing this.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-05-03 08:26:03 -04:00
Antara Borwankar 55b0b75bb9 fix: [Stage1B] Extending correct cfg data and hash length in tpm
length of external config data and hash keys extended to the TPM was
incorrect. This commit fixes this issue.

Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
2024-04-24 11:07:35 -07:00
Guo Dong c781b14a03 feat: Add FIT image support
New universal payload used FIT image format.
The spec defined https://universalpayload.github.io/spec/chapter2-payload-image-format.html
This change could boot FIT universal payload.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2024-04-24 09:32:51 -07:00
Yi Li 6adb9072d5 Let Stage1B run in memory accoss all stages in fast boot mode
This will increase time of Board PostMemoryInit hook and TempRamExit,
but improve the performance of PostTempRamExit hook, PreSiliconInit hook
and FSP-S.

In total, the boot time can be reduced by ~20ms.

Signed-off-by: Yi Li <yi1.li@intel.com>
2024-04-02 09:45:30 -07:00
aborwank 6875a3bdc9
feat: creating actm binary to be copied in build folder (#2141)
For platforms with seperate actm binary added code to
copy actm binary to build fv folder

Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
2024-03-21 21:21:13 -07:00
bejeanmo 9c527d99c8
fix: Only register root bridges with actual devices, not empty ones. (#2142)
Registering logical root bridges with no devices can cause unexpected
behavior for platforms that use _PCI_ENUM_BUS_SCAN_TYPE = "range", since
all empty buses in the range will be compared against the resource
allocation table entries.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-02-16 10:34:49 -07:00
bejeanmo fed94258ac
fix: Remove check for physical root bridge device before scanning. (#2140)
Not all root bridges have a physical device at dev 0 func 0 of the root
bus, and this requirement prevents some platforms from being fully scanned.
From this point, PciEnumerationLib doesn't access the root bridge
configuration space at all, so this is an unnecessary check.

Instead, root bus scanning will continue without dev 0 func 0 present. If
no devices are found on the root bus, scanning will continue to the next
root bridge.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-02-15 13:49:02 -07:00
aborwank 6ca7a860b9
Revert "fix: [TPM] correcting cfg data and key hash" (#2122)
This reverts commit 2f277eb9f1.

Due to entire binaries being dumped in eventlog, many event
getting skipped for space constraint. Hence reverting.

Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
2024-01-23 22:46:55 -07:00
Antara Borwankar 2f277eb9f1 fix: [TPM] correcting cfg data and key hash
issue: https://jira.devtools.intel.com/browse/IOTGSECSW-2031

Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
2024-01-22 10:09:15 -07:00
Bejean Mosher 1d38f8e69f feat: Validate BMP headers to protect against LogoFAIL.
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-01-08 15:04:47 -07:00
Chirag Vijay Kolhe 7e3a4cb601 fix: [Common] Fix debug message to print cpu state
Fixed debug message to print cpu index, APIC ID and cpu state in order.

Signed-off-by: Chirag Vijay Kolhe <chirag.vijay.kolhe@intel.com>
2023-12-14 15:57:57 -07:00
Guo Dong 4d5df7b913 feat: Fix the syntax warning
Fix the build warning using Python 3.12.
The warning message "SyntaxWarning: invalid escape sequence"

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-11-03 13:03:23 -07:00
Guo Dong caefea4df3 * feat: Fix the build failure with Python 3.12
distutils is deprecated in Python 3.10 and 3.11.
And it is removed in Python 3.12. So remove the
dependency.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-11-03 13:03:23 -07:00
Guo Dong 6570aa9037 Update FPDT Table
Update the FPDT header length to include the length
of boot records. This way we could easily get all the
boot records from dumped ACPI FPDT table.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-10-12 08:35:13 -07:00
Jiaqing Zhao ebc9ae0625 Container: Add new container type MULTIBOOT_MODULE
The MULTIBOOT_MODULE type indicates the container contains only
multiboot modules and their string without a bootable kernel. Similar
to the MULTIBOOT container type, the files in container should be
organized in pairs which contains a zero-teminated text for string
and the a module binary.

This type should only be used in Extra images when Normal image is in
multiboot/multiboot2 format.

Signed-off-by: Jiaqing Zhao <jiaqing.zhao@intel.com>
2023-09-12 13:55:06 -07:00
Guo Dong 9380ed2d0e Send FSP notification in universal UEFI payload
In current implementation all FSP notification are sent in SBL.
When using universal UEFI payload with SMM enabled, it is expected
to send ReadyToBoot and EndOfFirmware event in payload.
This patch just skip the FSP notification in SBL. Universal UEFI
payload should make sure FSP notification would be sent.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-09-05 20:30:51 -07:00
cshur 83e3f07c9d feat: Update # of X2Apic Processor Local APIC
Since # of PROCESSOR_LOCAL_APICs are
Madt Local Apic # is 1.
Madt X2 Local Apic # is 9.

Need to update # of structure type of X2Apic.

Signed-off-by: cshur <cs.hur@intel.com>
2023-09-05 15:48:55 -07:00
koktong-ong 2d18ee3a46
fix: [MTL] Add IgdOpRegionDefine 3.0 header (#2017)
Added IgdOpRegionDefine 3.0 header file
Removed unsed IgdPlatformInfo in Stage2BoardInit file

TEST: Booted into Ubuntu and Windows

Signed-off-by: Kobe <kok.tong.ong@intel.com>
2023-09-05 18:17:28 -04:00
Guo Dong 60c2df3de3 [TOOL]: Enhance build tool for CFG data
Currently the build tool always find the config data yaml file
from the brd_name path.
With this update, it will first search yaml file from
brd_name_override path,  if yaml file could not be found, then
it will search yaml file from brd_name path.
And currently it would generate ConfigDataStruct.h and
ConfigDataDynamic.h in brd_name path. With this change, generate
them in board common path.

With this change, full config data could be in brd_name or in
brd_name_override path.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-08-29 10:47:43 -07:00
Vincent Chen ec5c39e35a feat: [ADL] separate CfgDataDef.yaml for different PCH series
ADL groups GPIO pins into different sets for different PCH series.
The current CfgData uses ADLS's GPIO group sets as the base, and
overwrites the GrpIdx fields via DLT files for other PCH series.
This results in two issues:
1. "CfgDataTool.py export" command failed to extract DLT files
   from SBL image, since it cannot identify the proper group
   index in CfgDataExt.bin from the base table in CfgDataInt.bin
2. When using ConfigEditor.py to configure the PadGroup field of
   GPIO Payload Selection, it will map to a wrong group index.

This patch separates CfgDataDef.yaml for each of PCH series
- add _CFGDATA_DEF_FILE in BoardConfig.py
- add board extension yaml files for Adln, Adlp, Adls
  * CfgDataDef*.yaml
  * CfgData_Gpio_*.yaml
  * CfgData_PayloadSelection_*.yaml
- assign an invalid/unique GrpIdx for the unused GPIO group
  * e.g. 1F, 1E, ..
- adjust GrpIdx of CfgDataExt_Upx12.dlt based on Adlp
- revise the payload selection information in DLT files

This patch also fixes the issue:
- When ConfigEditor opens CfgDataDef.yaml more than once, the
  config changes will not be caught by "Save Config Changes to
  Delta File"
It is because the "info" argument of build_cfg_list() in
GenCfgData.py will retain its value in the lifetime of
ConfigEditor, and the offset will overflow. So need to reset
the offset for a fresh load_yaml().

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2023-08-24 09:52:21 -07:00
Sean McGinn 6e47ec2ade Resiliency support on MTL-P
Add support for resiliency on MTL-P
Increase the TCO timeout for all platforms to accomodate MTL-P
Clear 1st TCO timeout status bit along with 2nd TCO timeout status bit
Clear TCO timeout before changing it

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-08-16 12:00:11 -07:00
Sachin Kamat 2e2ceabafd fix: [PCIe] Fix assert check
Assert check was one off causing problem for corner cases.
Upated the check.

Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
2023-08-03 11:28:39 -07:00
Kevin Tsai 877ac9ffc9 fix: [Common] Fix Coverity issues
Resolved below issues.
Untrusted pointer read(CWE 129)
Operands don't affect result(CWE 569)
Unchecked return value(CWE 252)
Logically dead code(CWE 561)
Unused value(CWE 563)
Unintended sign extension(CWE 194)
Out-of-bounds access(CWE 119)

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-07-27 15:51:26 -07:00
tsaikevin 0d45c3e60a
fix: [Common] Fix Coverity issues (#1958)
Fixed dead default in switch and logically dead code (CWE 561)

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-07-19 14:03:41 -07:00
stanley 8cc2cab427
feat: [EHL] enable BoardNotifyPhase during FWU (#1939)
The FSP may request for a reboot when some features are
enable/disable. The SiliconInit FW update is one case for the
"FSP requested boot". Without the patch, SBL has no way to
get the notification from CallFspNotifyPhase.

The patch introduces a feature, PcdEnableFwuNotify,
to allow SBL to keep BoardNotifyPhase during firmware update.

On EHL, the feature can be enabled by "disable BIOS Lock".

Verify: EHL-CRB

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
2023-07-14 18:50:01 -04:00
Guo Dong 2b8ca86087
feat: fix Klocwork issue (#1947)
Fix the issue - Uninitialized Variable ResetVectorTime

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-06-29 11:45:42 -07:00
Guo Dong 475ff9daca
feat: Fix ACPI FPDT SBL boot performance (#1935)
In current code, BoardNotifyPhase() would update FPDT SBL performance
table in S3 path. It could cause S3 issue since PcdAcpiTablesRsdp is
not updated.
Move the FPDT related code to AcpiFpdt.c
Update FPDT SBL performance table in stage2 so that this table
could be updated for all payloads.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-06-25 21:06:43 -07:00
Atharva Lele 1d2e75b5be fix: resolve FPDT related Klocwork issues
- Add a null check for Rsdp pointer before accessing it
- Initialize ResetVectorTime, Time to some value before using it
- Add debug print for success / failure

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-06-18 16:42:21 -07:00
Sean McGinn b7b5221441 [RPL] Increase TCO timeout
Increase the TCO timeout as some platforms take longer
to boot

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-06-12 21:38:12 -07:00
Jiaqing Zhao f041c395c3 BootloaderCorePkg/Tools: PatchFv: Handle 32-bit address in GCC map
Some versions of ld (like 2.40 in Ubuntu 23.04) uses 32-bit address
when generating map files for IA32 build. This patch enables PatchFv.py
to parse these 32-bit addresses in GCC map properly.

Signed-off-by: Jiaqing Zhao <jiaqing.zhao@intel.com>
2023-06-12 12:14:44 -07:00
koktong-ong d7727bc60c
fix: [Common] Fix KW issues (#1920)
Fixed Klocwork issues

Signed-off-by: Kobe <kok.tong.ong@intel.com>
2023-06-12 09:09:25 -04:00
bejeanmo a34e54e175
feat: [FSP2.4] Added FSP variable serivices, Multi Phase Mem and SI. (#1901)
FSP 2.4 adds a requirement for Bootloader to respond to FSP Variable
requests in a way that is similar to UEFI variable services. This
implementation adds support for using the updated SBL VariableLib so that
the FspVariableServicesLib wrapper is no longer needed.

Additionally, support for Multi-Phase mem and SI init is added. FSP 2.4
introduces the mandatory MultiPhaseMemInit call, and makes the
MultiPhaseSiInit call mandatory where it was previously optional.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-05-24 14:36:35 -04:00
Stanley Chang 23d9187bde fix: [EHL] send EOP message
EHL FSP does not send EOP (End Of Post) message at the
Ready to Boot. The patch adds support for SBL to send
the EOP during Ready to Boot.

Verified: EHL CRB

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
2023-05-24 11:23:54 -07:00
Atharva Lele 3422681785
feat: add SBL boot performance data to FPDT (#1890)
Adds SBL boot performance data (Stage1 time, Stage 2 time, OsLoader time)
to the FPDT with type 0x3000 (Reserved for platform firmware Vendor usage)

Other fixes:
- Move logging of measure point 40F0 inside the condition for measured boot
- Add missing call to log measure point 40E0 used to log kernel setup print
  time

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-05-23 10:26:34 -07:00
Sean McGinn f9d614c09f Move MB/ACPI macros to BootloaderCommonLib
Move macros to BootloaderCommonLib as they
are now consumed by both SBL stages and payload

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
Barnes d8822031d9 [ALL Platforms] Update Build tools impact all
platforms

Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file

Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
2023-04-27 10:20:32 -07:00
Bejean Mosher 96f72c39b8 feat: FuSa Configuration library template, and ADL/RPL FuSa Cfg Data.
Added Null template for FusaConfigLib. Platforms supporting FuSa should
follow this template for enabling FuSa configuration prior to FSP-M and
FSP-S.

Added ADL/RPL CfgData fields for FuSa according to SBL FuSa software
requirements, and dlt file for enabling FuSa and related configuration.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-04-26 14:54:21 -07:00
Sean McGinn ca7c2796d1 Change Event Type and PCR Number for Extending Config Data into TPM PCR
Align event type and PCR number with BIOS implementation

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-28 15:55:01 -07:00
koktong-ong c7fbc86eb3
Added FspNonVolatileStorageHob2 support in FspSupportLib (#1850)
Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2

Signed-off-by: Kobe <kok.tong.ong@intel.com>
2023-03-24 08:33:10 -04:00
Atharva Lele 1c807e51fa
Fix OsLoader handling of non-container images and remove PcdContainerBootEnabled (#1843)
* OsLoader: set default status to EFI_UNSUPPORTED when parsing a boot image

This was set to EFI_SUCCESS which resulted in ParseBootImages() returning
EFI_SUCCESS even if the boot image was not a container or a component.

Thus, the boot would continue and fail at a later stage due to the
LoadedImage structure not being populated correctly.

Setting it to EFI_UNSUPPORTED will result in ParseBootImages() returning
EFI_UNSUPPORTED if a non-supported boot image is provided and OsLoader
will attempt to boot the next entry in the boot options list.

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Remove PcdContainerBootEnabled PCD

SBL requires boot images to be packaged as a container or a component

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

---------

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-03-10 14:14:13 -08:00
Sean McGinn f3d515cd32 Cast FW blob pointers to UINTN then UINT64
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-06 10:48:47 -07:00
Sean McGinn 11337871ca Get TPM2 event log working with SBL
For TPM2 event logging, whenever a EV_EFI_VARIABLE_DRIVER_CONFIG
type event is logged, the associated data is expected to be
structured as UEFI_VARIABLE_DATA. However, for key hash and
configuration data, the event data provided was given as a string.

This change corrects the event type for these regions as they
are not actually EFI variables.

This change also provides event data in the structure associated with
the correct event type.

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-06 10:48:47 -07:00
Bejean Mosher 7942790d76 fix: [ADL/RPL] Move NVME boot option update to PCI Enumeration hook.
Re-scanning PCI devices to find NVME controllers was adding an additional
~20ms to the end of Stage 2. Moving this to the existing PCI scan that
is part of PCI enumeration saves this time. However, this
EfiPciBeforeResourceCollection phase was not actually getting called and
needed to be added.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-02-22 15:19:56 -07:00
Vincent Chen 4f28bcd493
fix: correct the default key for signing BOOT container (#1830)
When GenContainer.py extracts a container image, a layout file
is created that specifies the format of header and components.
For container header with BOOT name, the signing key is expected
to be KEY_ID_OS1_PRIVATE. Correct it for not misleading.

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2023-02-09 15:04:22 -08:00
bejeanmo b9057d0bd1
feat: Add support for FSP Reset request value in ResetSystemLib. (#1825)
Silicon Reset Lib needs to know the FSP reset request status since some
FSPs will utilize Reset values besides warm/cold.

Added support for ADl/RPL global reset request from FSP.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-02-03 16:49:18 -05:00
Sean McGinn 6baff56e60 Replace shutdown with TCO timer stop and CPU halt
This change converts a shutdown to a TCO timer stop and
CPU halt as shutdown was discovered to be empty (and thus
the same as CPU halt).

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-01-04 10:21:47 -07:00