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[TGL] Rename LowPowerS0Idle to S0ix 

For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- enable s0ix by default for TGL-U
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This commit is contained in:
Lean Sheng Tan 2021-08-11 02:31:55 +08:00 committed by Aiden Park
parent a7063eb30a
commit e7a47908b4
6 changed files with 46 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Platform/TigerlakeBoardPkg/CfgData/CfgData_Features.yaml
View File

@ -2,7 +2,7 @@
#
# Slim Bootloader CFGDATA Option File.
#
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@ -34,12 +34,12 @@
help : >
Enable/Disable MeasuredBoot feature. 1:MeasuredBoot Enabled (default), 0:MeasuredBoot Disabled
length : 1b
- LowPowerS0Idle :
name : Low Power S0 Idle Enable (S0ix)
- S0ix :
name : S0ix (Low Power S0 Idle) Enable
type : Combo
option : $EN_DIS
help : >
Enable/Disable Low Power Idle feature. 1:Low Power S0 Idle Enabled, 0:Low Power S0 Idle Disabled
Enable/Disable S0ix feature. 1:S0ix Enabled, 0:S0ix Disabled
length : 1b
- FusaEnable :
name : Fusa Enable

3
Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4.dlt
View File

@ -11,6 +11,9 @@
PLATFORMID_CFG_DATA.PlatformId | 0x0001
PLAT_NAME_CFG_DATA.PlatformName | 'TGLU_DDR'
# Enable S0ix by default
FEATURES_CFG_DATA.Features.S0ix | 0x1
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch1 | {0, 1}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3 | {0, 1}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch0 | {0, 1}

4
Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_DdrLp4.dlt
View File

@ -11,6 +11,10 @@
# DDRLP4 board
PLATFORMID_CFG_DATA.PlatformId | 0x0003
PLAT_NAME_CFG_DATA.PlatformName | 'TGLU_LP4'
# Enable S0ix by default
FEATURES_CFG_DATA.Features.S0ix | 0x1
MEMORY_CFG_DATA.SpdAddressTable | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
MEMORY_CFG_DATA.SpdDataSel000 | 1
MEMORY_CFG_DATA.SpdDataSel010 | 1

41
Platform/TigerlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -117,6 +117,7 @@ TccModePreMemConfig (
FspmUpd->FspmConfig.HyperThreading = PolicyConfig->HyperThreading;
FspmUpd->FspmConfig.PowerDownMode = PolicyConfig->MemPowerDown;
FspmUpd->FspmConfig.DisPgCloseIdleTimeout = PolicyConfig->DisPgCloseIdle;
PLAT_FEAT.S0ixEnable = PolicyConfig->Sstates;
DEBUG ((DEBUG_INFO, "Dump TCC DSO BIOS settings:\n"));
DumpHex (2, 0, sizeof(BIOS_SETTINGS), PolicyConfig);
}
@ -447,10 +448,6 @@ UpdateFspConfig (
Fspmcfg->VtdBaseAddress[6] = 0xfed87000;
}
// Update TCC related UPDs if TCC is enabled
if (FeaturePcdGet (PcdTccEnabled)) {
TccModePreMemConfig (FspmUpd);
}
Fspmcfg->BootFrequency = 0x2;
// will hang using default upds
@ -486,23 +483,29 @@ UpdateFspConfig (
Fspmcfg->CpuPcieRpEnableMask = 0;
}
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
if ((FeaturesCfgData != NULL) && (FeaturesCfgData->Features.LowPowerS0Idle == 1)) {
Fspmcfg->TcssXdciEn=0;
Fspmcfg->TcssXhciEn=0;
Fspmcfg->TcssDma0En=0;
Fspmcfg->TcssDma1En=0;
Fspmcfg->TcssItbtPcie0En=0;
Fspmcfg->TcssItbtPcie1En=0;
Fspmcfg->TcssItbtPcie2En=0;
Fspmcfg->TcssItbtPcie3En=0;
Fspmcfg->DmiAspmCtrl = 2;// ASPM configuration on the CPU side of the DMI/OPI Link
// s0ix update
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag (CDATA_FEATURES_TAG);
if (FeaturesCfgData != NULL) {
PLAT_FEAT.S0ixEnable = FeaturesCfgData->Features.S0ix;
}
/*Fspmcfg->PlatformDebugConsent=2; // Enable DCI and DAM for CCA
Fspmcfg->DciEn=1;
Fspmcfg->PchTraceHubMode=2;
Fspmcfg->CpuTraceHubMode=2;*/
// Update TCC related UPDs if TCC is enabled
if (FeaturePcdGet (PcdTccEnabled)) {
TccModePreMemConfig (FspmUpd);
}
if (S0IX_STATUS() == 1) {
// configure s0ix related FSP-M UPDs
Fspmcfg->TcssXdciEn = 0;
Fspmcfg->TcssXhciEn = 0;
Fspmcfg->TcssDma0En = 0;
Fspmcfg->TcssDma1En = 0;
Fspmcfg->TcssItbtPcie0En = 0;
Fspmcfg->TcssItbtPcie1En = 0;
Fspmcfg->TcssItbtPcie2En = 0;
Fspmcfg->TcssItbtPcie3En = 0;
Fspmcfg->DmiAspmCtrl = 2;// ASPM configuration on the CPU side of the DMI/OPI Link
}
}
/**

22
Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -84,7 +84,6 @@
BOOLEAN mTccDsoTuning = FALSE;
UINT8 mTccRtd3Support = 0;
UINT8 mTccLowPowerS0Idle = 0;
//
// The EC implements an embedded controller interface at ports 0x60/0x64 and a ACPI compliant
@ -1219,7 +1218,6 @@ TccModePostMemConfig (
FspsUpd->FspsConfig.CpuPcieRpL1Substates[Index] = PolicyConfig->CpuPcieRpL1;
}
mTccRtd3Support = PolicyConfig->Dstates;
mTccLowPowerS0Idle = PolicyConfig->Sstates;
mTccDsoTuning = TRUE;
}
}
@ -1275,7 +1273,6 @@ UpdateFspConfig (
FSPS_UPD *FspsUpd;
SECURITY_CFG_DATA *SecCfgData;
SILICON_CFG_DATA *SiCfgData;
FEATURES_CFG_DATA *FeaturesCfgData;
FSP_S_CONFIG *FspsConfig;
UINT8 Index;
UINT8 PrIndex;
@ -1622,8 +1619,7 @@ UpdateFspConfig (
FspsUpd->FspsConfig.RtcBiosInterfaceLock = TRUE;
}
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
if ((FeaturesCfgData != NULL) && (FeaturesCfgData->Features.LowPowerS0Idle == 1)) {
if (S0IX_STATUS() == 1) {
FspsConfig->C1e = 1;
FspsConfig->Cx = 1;
FspsConfig->PkgCStateLimit = 8;
@ -2148,7 +2144,6 @@ PlatformUpdateAcpiTable (
PLATFORM_DATA *PlatformData;
TCC_CFG_DATA *TccCfgData;
SILICON_CFG_DATA *SiCfgData;
FEATURES_CFG_DATA *FeaturesCfgData;
MEMORY_CFG_DATA *MemCfgData;
UINTN DmarTableFlags;
VOID *FspHobList;
@ -2250,9 +2245,9 @@ PlatformUpdateAcpiTable (
(((ACPI_LOW_POWER_IDLE_TABLE *)Table)->LpiStates[LpitStateEntries - 1].ResidencyCounter) = SetResidencyCounter[0];
(((ACPI_LOW_POWER_IDLE_TABLE *)Table)->LpiStates[LpitStateEntries - 1].ResidencyCounterFrequency) = ResidencyCounterFrequency;
}
} else if (Table->Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
if ((FeaturesCfgData != NULL) && (FeaturesCfgData->Features.LowPowerS0Idle == 1)) {
}
else if (Table->Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
if (S0IX_STATUS() == 1) {
EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *FadtTable;
DEBUG ((DEBUG_INFO, "Update FADT ACPI table\n"));
FadtTable = (EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE*) Table;
@ -2565,7 +2560,6 @@ PlatformUpdateAcpiGnvs (
SYSTEM_AGENT_NVS_AREA *SaNvs;
SYS_CPU_INFO *SysCpuInfo;
SILICON_CFG_DATA *SiCfgData;
FEATURES_CFG_DATA *FeaturesCfgData;
EFI_CPUID_REGISTER CpuidRegs;
UINT8 Index;
UINT8 Length;
@ -2707,10 +2701,8 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->Rtd3Support = 1;
PlatformNvs->TenSecondPowerButtonEnable = 0x9;
PlatformNvs->HidEventFilterEnable = 0x01;
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
if (FeaturesCfgData != NULL) {
PlatformNvs->LowPowerS0Idle = (UINT8) (FeaturesCfgData->Features.LowPowerS0Idle);
}
PlatformNvs->LowPowerS0Idle = S0IX_STATUS();
// Bit[1:0] - Storage (0:None, 1:Adapter D0/F1, 2:Raid, 3:Adapter D3)
// Bit[2] - En/Dis UART0
// Bit[3] - En/Dis UART1
@ -3015,7 +3007,5 @@ PlatformUpdateAcpiGnvs (
// If TCC is enabled, use the TCC policy from subregion
if (mTccDsoTuning) {
PlatformNvs->Rtd3Support = mTccRtd3Support;
PlatformNvs->LowPowerS0Idle = mTccLowPowerS0Idle;
}
}

9
Silicon/TigerlakePkg/Include/PlatformData.h
View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -21,7 +21,8 @@ typedef struct {
typedef struct {
UINT32 VtdEnable : 1;
UINT32 Rsvd : 31;
UINT32 S0ixEnable : 1;
UINT32 Rsvd : 30;
} PLAT_FEATURES;
typedef struct {
@ -29,4 +30,8 @@ typedef struct {
PLAT_FEATURES PlatformFeatures;
} PLATFORM_DATA;
#define PLAT_DATA ((PLATFORM_DATA *)GetPlatformDataPtr ())
#define PLAT_FEAT (PLAT_DATA->PlatformFeatures)
#define S0IX_STATUS() (BOOLEAN) (PLAT_FEAT.S0ixEnable)
#endif /* __PLATFORM_DATA_H__ */