OrgACRN
/
slimbootloader
mirror of https://github.com/slimbootloader/slimbootloader.git
1
0
Fork 0
Code Issues Releases Wiki Activity

[TGL] Add TCC GPIO support 

Add SBL configuration data for TCC GPIO.
Update TCC GPIO UPD and ACPI NVS data based
on SBL configuration data.

Signed-off-by: Guo Dong <guo.dong@intel.com>
This commit is contained in:
Guo Dong 2021-01-24 21:22:31 -07:00 committed by James Gutbub
parent 5782673871
commit 1ca2058a95
4 changed files with 37 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4_Tcc_Mode.dlt
View File

@ -31,6 +31,9 @@ MEMORY_CFG_DATA.DmaControlGuarantee | 1
CAPSULE_INFO_CFG_DATA.DevType | 6 CAPSULE_INFO_CFG_DATA.DevType | 6
FEATURES_CFG_DATA.Features.Tcc | 1 FEATURES_CFG_DATA.Features.Tcc | 1
SILICON_CFG_DATA.EnableTimedGpio0 | 1
SILICON_CFG_DATA.EnableTimedGpio1 | 1
# #
# To enable payload selection the below options need to uncommented. # To enable payload selection the below options need to uncommented.
# This GPIO maps to pins 3/4 on 4-pin jumper J9J5 which is closest # This GPIO maps to pins 3/4 on 4-pin jumper J9J5 which is closest

3
Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_DdrLp4_Tcc_Mode.dlt
View File

@ -25,6 +25,9 @@ GEN_CFG_DATA.PayloadId | 'UEFI'
CAPSULE_INFO_CFG_DATA.DevType | 6 CAPSULE_INFO_CFG_DATA.DevType | 6
FEATURES_CFG_DATA.Features.Tcc | 1 FEATURES_CFG_DATA.Features.Tcc | 1
SILICON_CFG_DATA.EnableTimedGpio0 | 1
SILICON_CFG_DATA.EnableTimedGpio1 | 1
# #
# To enable payload selection the below options need to uncommented. # To enable payload selection the below options need to uncommented.
# This GPIO maps to pins 3/4 on 4-pin jumper J9J5 which is closest # This GPIO maps to pins 3/4 on 4-pin jumper J9J5 which is closest

26
Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml
View File

@ -220,6 +220,30 @@
Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0- disable, 1- enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0- disable, 1- enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.
length : 0x04 length : 0x04
value : { 0x01, 0x01, 0x01, 0x01 } value : { 0x01, 0x01, 0x01, 0x01 }
- XdciEnable :
name : xDCI controller
type : Combo
option : $EN_DIS
help : >
Enable/disable to xDCI controller. 0- Disable; 1- Enable.
length : 0x01
value : 0x1
- EnableTimedGpio0 :
name : Timed GPIO 0
type : Combo
option : $EN_DIS
help : >
Enable/disable Timed GPIO0 0- Disable; 1- Enable.
length : 0x01
value : 0x0
- EnableTimedGpio1 :
name : Timed GPIO 1
type : Combo
option : $EN_DIS
help : >
Enable/disable Timed GPIO1 0- Disable; 1- Enable.
length : 0x01
value : 0x0
- ConfigTdpLevel : - ConfigTdpLevel :
name : Configuration for boot TDP selection name : Configuration for boot TDP selection
type : EditNum, HEX, (0x00, 0xFF) type : EditNum, HEX, (0x00, 0xFF)
@ -228,6 +252,6 @@
length : 0x01 length : 0x01
value : 0x02 value : 0x02
- Dummy : - Dummy :
length : 0x0 length : 0x1
value : 0x0 value : 0x0

7
Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -1653,7 +1653,6 @@ UpdateFspConfig (
FspsConfig->PortUsb30Enable[1] = 0x1; FspsConfig->PortUsb30Enable[1] = 0x1;
FspsConfig->PortUsb30Enable[2] = 0x1; FspsConfig->PortUsb30Enable[2] = 0x1;
FspsConfig->PortUsb30Enable[3] = 0x1; FspsConfig->PortUsb30Enable[3] = 0x1;
FspsConfig->XdciEnable = 0x1;
if (IsPchH ()) { if (IsPchH ()) {
FspsConfig->PortUsb20Enable[1] = 0x1; FspsConfig->PortUsb20Enable[1] = 0x1;
@ -1724,6 +1723,9 @@ UpdateFspConfig (
if (SiCfgData != NULL) { if (SiCfgData != NULL) {
FspsConfig->ConfigTdpLevel = SiCfgData->ConfigTdpLevel; FspsConfig->ConfigTdpLevel = SiCfgData->ConfigTdpLevel;
FspsConfig->EnableTimedGpio0 = SiCfgData->EnableTimedGpio0;
FspsConfig->EnableTimedGpio1 = SiCfgData->EnableTimedGpio1;
FspsConfig->XdciEnable = SiCfgData->XdciEnable;
} }
Status = TccModePostMemConfig (FspsUpd); Status = TccModePostMemConfig (FspsUpd);
@ -2653,6 +2655,9 @@ PlatformUpdateAcpiGnvs (
PchNvs->SWMC = GetPchHdaMaxSndwLinkNum(); PchNvs->SWMC = GetPchHdaMaxSndwLinkNum();
Length = GetPchMaxPciePortNum (); Length = GetPchMaxPciePortNum ();
PchNvs->EnableTimedGpio0 = FspsConfig->EnableTimedGpio0;
PchNvs->EnableTimedGpio1 = FspsConfig->EnableTimedGpio1;
PchMaxPciePortNum = GetPchMaxPciePortNum (); PchMaxPciePortNum = GetPchMaxPciePortNum ();
for (Index = 0; Index < PchMaxPciePortNum; Index++) { for (Index = 0; Index < PchMaxPciePortNum; Index++) {
PchNvs->LtrEnable[Index] = FspsConfig->PcieRpLtrEnable[Index]; PchNvs->LtrEnable[Index] = FspsConfig->PcieRpLtrEnable[Index];