diff --git a/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4_Tcc_Mode.dlt b/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4_Tcc_Mode.dlt
index a7f6bc84..570d4bae 100644
--- a/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4_Tcc_Mode.dlt
+++ b/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4_Tcc_Mode.dlt
@@ -31,6 +31,9 @@ MEMORY_CFG_DATA.DmaControlGuarantee | 1
 CAPSULE_INFO_CFG_DATA.DevType | 6
 FEATURES_CFG_DATA.Features.Tcc | 1
 
+SILICON_CFG_DATA.EnableTimedGpio0 | 1
+SILICON_CFG_DATA.EnableTimedGpio1 | 1
+
 #
 # To enable payload selection the below options need to uncommented.
 # This GPIO maps to pins 3/4 on 4-pin jumper J9J5 which is closest
diff --git a/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_DdrLp4_Tcc_Mode.dlt b/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_DdrLp4_Tcc_Mode.dlt
index 18d3d08a..bcb15a74 100644
--- a/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_DdrLp4_Tcc_Mode.dlt
+++ b/Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_DdrLp4_Tcc_Mode.dlt
@@ -25,6 +25,9 @@ GEN_CFG_DATA.PayloadId                   | 'UEFI'
 CAPSULE_INFO_CFG_DATA.DevType | 6
 FEATURES_CFG_DATA.Features.Tcc | 1
 
+SILICON_CFG_DATA.EnableTimedGpio0 | 1
+SILICON_CFG_DATA.EnableTimedGpio1 | 1
+
 #
 # To enable payload selection the below options need to uncommented.
 # This GPIO maps to pins 3/4 on 4-pin jumper J9J5 which is closest
diff --git a/Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml b/Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml
index 6beafb7d..04e245d0 100644
--- a/Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml
+++ b/Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml
@@ -220,6 +220,30 @@
                      Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0- disable, 1- enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.
       length       : 0x04
       value        : { 0x01, 0x01, 0x01, 0x01 }
+  - XdciEnable :
+      name         : xDCI controller
+      type         : Combo
+      option       : $EN_DIS
+      help         : >
+                     Enable/disable to xDCI controller. 0- Disable; 1- Enable.
+      length       : 0x01
+      value        : 0x1
+  - EnableTimedGpio0 :
+      name         : Timed GPIO 0
+      type         : Combo
+      option       : $EN_DIS
+      help         : >
+                     Enable/disable Timed GPIO0    0- Disable; 1- Enable.
+      length       : 0x01
+      value        : 0x0
+  - EnableTimedGpio1 :
+      name         : Timed GPIO 1
+      type         : Combo
+      option       : $EN_DIS
+      help         : >
+                     Enable/disable Timed GPIO1    0- Disable; 1- Enable.
+      length       : 0x01
+      value        : 0x0
   - ConfigTdpLevel :
       name         : Configuration for boot TDP selection
       type         : EditNum, HEX, (0x00, 0xFF)
@@ -228,6 +252,6 @@
       length       : 0x01
       value        : 0x02
   - Dummy        :
-      length       : 0x0
+      length       : 0x1
       value        : 0x0
 
diff --git a/Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c b/Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
index af05e310..bd348686 100644
--- a/Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
+++ b/Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
@@ -1653,7 +1653,6 @@ UpdateFspConfig (
   FspsConfig->PortUsb30Enable[1] = 0x1;
   FspsConfig->PortUsb30Enable[2] = 0x1;
   FspsConfig->PortUsb30Enable[3] = 0x1;
-  FspsConfig->XdciEnable = 0x1;
 
   if (IsPchH ()) {
     FspsConfig->PortUsb20Enable[1] = 0x1;
@@ -1724,6 +1723,9 @@ UpdateFspConfig (
 
   if (SiCfgData != NULL) {
     FspsConfig->ConfigTdpLevel = SiCfgData->ConfigTdpLevel;
+    FspsConfig->EnableTimedGpio0 = SiCfgData->EnableTimedGpio0;
+    FspsConfig->EnableTimedGpio1 = SiCfgData->EnableTimedGpio1;
+    FspsConfig->XdciEnable       = SiCfgData->XdciEnable;
   }
   Status = TccModePostMemConfig (FspsUpd);
 
@@ -2653,6 +2655,9 @@ PlatformUpdateAcpiGnvs (
   PchNvs->SWMC = GetPchHdaMaxSndwLinkNum();
   Length = GetPchMaxPciePortNum ();
 
+  PchNvs->EnableTimedGpio0 = FspsConfig->EnableTimedGpio0;
+  PchNvs->EnableTimedGpio1 = FspsConfig->EnableTimedGpio1;
+
   PchMaxPciePortNum = GetPchMaxPciePortNum ();
   for (Index = 0; Index < PchMaxPciePortNum; Index++) {
     PchNvs->LtrEnable[Index]                = FspsConfig->PcieRpLtrEnable[Index];