61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Liu Xinyun <xinyun.liu@intel.com>
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Date: Tue, 7 May 2019 21:47:23 +0800
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Subject: [PATCH] drm/i915/gvt: enable local direct display for WaaG
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align the display type with the one in the virtual vbt and add missing
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handler for sprite plane.
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Guest OS (Windows 10, eg) which has no idea of the plane restriction can
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output to a local monitor with a specific service OS now. The SOS should
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enable the plane restriction feature and leaves the first pipes for
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the guest OS.
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v1: separated from the previous patch enabling opregion
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Tracked-On: projectacrn/acrn-hypervisor#3106
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Signed-off-by: Liu Xinyun <xinyun.liu@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/display.c | 2 +-
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drivers/gpu/drm/i915/gvt/handlers.c | 10 +++-------
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2 files changed, 4 insertions(+), 8 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
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index 10736ee5cf44..1c905d9e063b 100644
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--- a/drivers/gpu/drm/i915/gvt/display.c
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+++ b/drivers/gpu/drm/i915/gvt/display.c
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@@ -569,7 +569,7 @@ void intel_gvt_init_pipe_info(struct intel_gvt *gvt)
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}
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}
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-bool gvt_emulate_hdmi = true;
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+bool gvt_emulate_hdmi;
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int setup_virtual_monitors(struct intel_vgpu *vgpu)
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{
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index 02c12fbeafd3..5eeb655edfaf 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -3129,13 +3129,9 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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MMIO_PLANES_DH(PLANE_AUX_DIST, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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MMIO_PLANES_DH(PLANE_AUX_OFFSET, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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- if (i915_modparams.avail_planes_per_pipe) {
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- MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL, NULL);
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- MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, NULL);
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- } else {
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- MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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- MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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- }
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+ MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL,
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+ skl_plane_mmio_write);
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+ MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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MMIO_PLANES_DH(PLANE_NV12_BUF_CFG, D_SKL_PLUS, NULL,
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pv_plane_wm_mmio_write);
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--
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https://clearlinux.org
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