From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Liu Xinyun Date: Tue, 7 May 2019 21:47:23 +0800 Subject: [PATCH] drm/i915/gvt: enable local direct display for WaaG align the display type with the one in the virtual vbt and add missing handler for sprite plane. Guest OS (Windows 10, eg) which has no idea of the plane restriction can output to a local monitor with a specific service OS now. The SOS should enable the plane restriction feature and leaves the first pipes for the guest OS. v1: separated from the previous patch enabling opregion Tracked-On: projectacrn/acrn-hypervisor#3106 Signed-off-by: Liu Xinyun Reviewed-by: Zhao Yakui --- drivers/gpu/drm/i915/gvt/display.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 10736ee5cf44..1c905d9e063b 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -569,7 +569,7 @@ void intel_gvt_init_pipe_info(struct intel_gvt *gvt) } } -bool gvt_emulate_hdmi = true; +bool gvt_emulate_hdmi; int setup_virtual_monitors(struct intel_vgpu *vgpu) { diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 02c12fbeafd3..5eeb655edfaf 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -3129,13 +3129,9 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_PLANES_DH(PLANE_AUX_DIST, D_SKL_PLUS, NULL, skl_plane_mmio_write); MMIO_PLANES_DH(PLANE_AUX_OFFSET, D_SKL_PLUS, NULL, skl_plane_mmio_write); - if (i915_modparams.avail_planes_per_pipe) { - MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL, NULL); - MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, NULL); - } else { - MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL, skl_plane_mmio_write); - MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, skl_plane_mmio_write); - } + MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL, + skl_plane_mmio_write); + MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, skl_plane_mmio_write); MMIO_PLANES_DH(PLANE_NV12_BUF_CFG, D_SKL_PLUS, NULL, pv_plane_wm_mmio_write); -- https://clearlinux.org