c3e67ad6f5
Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx
and RZ/G2L HW(Rev.0.50) manual.
Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and
separate reset from module clocks in order to handle them efficiently.
Update the SCIF0 clock and reset index in the SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com
[geert: Squashed 3 commits]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
||
|---|---|---|
| .. | ||
| arm | ||
| bus | ||
| clk | ||
| clock | ||
| display | ||
| dma | ||
| firmware/imx | ||
| gce | ||
| gpio | ||
| i2c | ||
| iio | ||
| input | ||
| interconnect | ||
| interrupt-controller | ||
| leds | ||
| mailbox | ||
| media | ||
| memory | ||
| mfd | ||
| mips | ||
| mux | ||
| net | ||
| phy | ||
| pinctrl | ||
| pmu | ||
| power | ||
| pwm | ||
| regulator | ||
| reset | ||
| reset-controller | ||
| soc | ||
| sound | ||
| spmi | ||
| thermal | ||
| usb | ||