178 lines
7.2 KiB
C
178 lines
7.2 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*_
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* Emulate a PCI Host bridge:
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* Intel Corporation Celeron N3350/Pentium N4200/Atom E3900
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* Series Host Bridge (rev 0b)
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*/
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#include <vm.h>
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#include <pci.h>
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#include "vpci_priv.h"
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#include <vacpi.h>
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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*/
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/* The chart below shows the hostbridge DID high-byte of the platform later than broadwell, whose PCIEXBAR are always
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located in the PCI hostbridge config space at the offset 0x60. This chart may need further extension in the future
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--------------------------------------------------------------------------------------
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platform | hostbridge DID high-byte
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--------------------------------------------------------------------------------------
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SKL(6-gen) | 0x19
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APL(6-gen Atom) | 0x5a
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KBL(7/8-gen) | 0x59
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CFL/CFL-R(8/9-gen) | 0x3e
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ICL(10-gen) | 0x9b
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EHL(11-gen) | 0x45
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TGL(11-gen) | 0x9a
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--------------------------------------------------------------------------------------
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*/
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static const uint32_t hostbridge_did_highbytes[] = {0x19U, 0x5aU, 0x59U, 0x3eU, 0x9aU, 0x45U, 0x9bU};
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/*
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The vhostbridge we currently emulated is "Celeron N3350/Pentium N4200/Atom E3900 Series Host Bridge",
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which belongs to Intel Appollo Lake processors family, and the device id is 5af0
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TODO:
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1. In the future, we may add one or more virtual hostbridges for CPUs that are incompatible in layout with the current one
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2. Besides PCIEXBAR(0x60), there are also some registers needs to be emulated more precisely rather than be treated as read-only and hard-coded, listed below:
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----------------------------------------------------------------------------------------------------------------
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reg | offset | length | current status | remark
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----------------------------------------------------------------------------------------------------------------
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STATUS_COMMAND | 0x8 | dword | unemulated | pci status and command
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SVID_SID | 0x2C | dword | unemulated | subsys id and subsys vendor id
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MCHBAR | 0x48 | qword | hard-coded | BAR of memory controller hub
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GGC | 0x50 | dword | hard-coded | graphics & mem controller hub graphics CR
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DEVEN | 0x54 | dword | hard-coded | device enable register
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PAVPC | 0x58 | dword | hard-coded | protected audio video path control
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TOUUD | 0xA8 | qword | hard-coded | top of upper usable DRAM
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BDSM | 0xB0 | dword | hard-coded | base of data stolen memory
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BGSM | 0xB4 | dword | hard-coded | base of graphics stolen memory
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TSEGMB | 0xB8 | dword | hard-coded | top segmentmemory base
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TOLUD | 0xBC | dword | hard-coded | top of lower usable dram
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SKPD | 0xDC | dword | unemulated | scratchpad
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CAPID0_CAPCTRL0 | 0xe0 | dword | hard-coded | capability 0 control
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----------------------------------------------------------------------------------------------------------------
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*/
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static void init_vhostbridge(struct pci_vdev *vdev)
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{
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union pci_bdf hostbridge_bdf = {.value = 0x0U};
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uint32_t pciexbar_low = 0x0U, pciexbar_high = 0x0U, phys_did, i;
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/* PCI config space */
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pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, 0x8086U);
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pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, 0x5af0U);
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pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0xbU);
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pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, (PCIM_HDRTYPE_NORMAL | PCIM_MFDEV));
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pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
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pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_HOST);
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pci_vdev_write_vcfg(vdev, 0x34U, 1U, 0xe0U);
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pci_vdev_write_vcfg(vdev, 0x3cU, 1U, 0xe0U);
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pci_vdev_write_vcfg(vdev, 0x48U, 4U, 0xfed10001U);
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pci_vdev_write_vcfg(vdev, 0x50U, 4U, 0x000002c1U);
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pci_vdev_write_vcfg(vdev, 0x54U, 4U, 0x00000033U);
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pci_vdev_write_vcfg(vdev, 0x58U, 4U, 0x7ff00007U);
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pci_vdev_write_vcfg(vdev, 0xa8U, 4U, 0x80000000U);
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pci_vdev_write_vcfg(vdev, 0xacU, 4U, 0x00000002U);
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pci_vdev_write_vcfg(vdev, 0xb0U, 4U, 0x7c000001U);
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pci_vdev_write_vcfg(vdev, 0xb4U, 4U, 0x7b800001U);
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pci_vdev_write_vcfg(vdev, 0xb8U, 4U, 0x7b000001U);
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pci_vdev_write_vcfg(vdev, 0xbcU, 4U, 0x80000001U);
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pci_vdev_write_vcfg(vdev, 0xe0U, 4U, 0x010c0009U);
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pci_vdev_write_vcfg(vdev, 0xf4U, 4U, 0x011c0f00U);
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if (is_prelaunched_vm(container_of(vdev->vpci, struct acrn_vm, vpci))) {
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/* For pre-launched VMs, we only need to write an GPA that's reserved in guest ve820,
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* and UOS_VIRT_PCI_MMCFG_BASE(0xE0000000) is fine. The trailing 1 is a ECAM enable-bit
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*/
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pciexbar_low = UOS_VIRT_PCI_MMCFG_BASE | 0x1U;
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}
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else {
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/*Inject physical ECAM value to SOS vhostbridge since SOS may check PCIe-MMIO Base Address with it */
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phys_did = pci_pdev_read_cfg(hostbridge_bdf, PCIR_DEVICE, 2);
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for (i = 0U; i < (sizeof(hostbridge_did_highbytes) / sizeof(uint32_t)); i++){
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if (((phys_did & 0xff00U) >> 8) == hostbridge_did_highbytes[i]) {
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/* The offset of PCIEXBAR register is 0x60 on Intel platforms, and no counter-case is encountered yet */
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pciexbar_low = pci_pdev_read_cfg(hostbridge_bdf, 0x60U, 4);
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pciexbar_high = pci_pdev_read_cfg(hostbridge_bdf, 0x64U, 4);
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break;
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}
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}
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}
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pci_vdev_write_vcfg(vdev, 0x60U, 4, pciexbar_low);
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pci_vdev_write_vcfg(vdev, 0x64U, 4, pciexbar_high);
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vdev->parent_user = NULL;
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vdev->user = vdev;
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}
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static void deinit_vhostbridge(__unused struct pci_vdev *vdev)
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{
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vdev->parent_user = NULL;
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vdev->user = NULL;
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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*/
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static int32_t read_vhostbridge_cfg(const struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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*val = pci_vdev_read_vcfg(vdev, offset, bytes);
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return 0;
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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*/
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static int32_t write_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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if (!is_bar_offset(PCI_BAR_COUNT, offset)) {
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pci_vdev_write_vcfg(vdev, offset, bytes, val);
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}
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return 0;
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}
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const struct pci_vdev_ops vhostbridge_ops = {
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.init_vdev = init_vhostbridge,
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.deinit_vdev = deinit_vhostbridge,
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.write_vdev_cfg = write_vhostbridge_cfg,
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.read_vdev_cfg = read_vhostbridge_cfg,
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};
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