acrn-hypervisor/hypervisor/dm/vpci
Li Fei1 a2fd8c5a9d pci: mcfg: limit device bus numbers which could access by ECAM
Per PCI Firmware Specification Revision 3.0, 4.1.2. MCFG Table Description:
Memory Mapped Enhanced Configuration Space Base Address Allocation Structure
assign the Start Bus Number and the End Bus Number which could decoded by the
Host Bridge. We should not access the PCI device which bus number outside of
the range of [Start Bus Number, End Bus Number).
For ACRN,  we should:
1. Don't detect PCI device which bus number outside the range of
[Start Bus Number, End Bus Number) of MCFG ACPI Table.
2. Only trap the ECAM MMIO size: [MMCFG_BASE_ADDRESS, MMCFG_BASE_ADDRESS +
(End Bus Number - Start Bus Number + 1) * 0x100000) for SOS.

Tracked-On: #5233

Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-09-09 09:31:56 +08:00
..
ivshmem.c hv: implement ivshmem device creation and destruction 2020-08-28 16:53:12 +08:00
pci_pt.c hv: code cleanup for vBAR writing 2020-08-19 15:06:15 +08:00
vdev.c HV: refine pci_find_vdev with hash 2020-06-18 12:58:40 +08:00
vhostbridge.c pci: mcfg: limit device bus numbers which could access by ECAM 2020-09-09 09:31:56 +08:00
vmsi.c HV: correct RO mask of MSI cap structure 2020-08-03 13:40:27 +08:00
vmsix.c hv: vpci: minor refine about MSI/MSI-X de-initialization 2020-07-02 13:03:36 +08:00
vmsix_on_msi.c hv: vmsi: add vmsix on msi emulation support 2020-06-16 08:52:56 +08:00
vpci.c pci: mcfg: limit device bus numbers which could access by ECAM 2020-09-09 09:31:56 +08:00
vpci_bridge.c hv: vpci: minor refine the vdev ownership data structure 2020-05-13 14:31:01 +08:00
vpci_priv.h hv: code cleanup for vBAR writing 2020-08-19 15:06:15 +08:00
vsriov.c HV: vdev passthough hidding SRIOV 2020-07-16 17:27:18 +08:00