197 lines
5.8 KiB
C
197 lines
5.8 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef INSTR_EMUL_WRAPPER_H
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#define INSTR_EMUL_WRAPPER_H
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#include <cpu.h>
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struct vie_op {
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uint8_t op_byte; /* actual opcode byte */
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_INST_SIZE 15
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struct vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t addrsize:4, opsize:4; /* address and operand sizes */
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1,
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repz_present:1, /* REP/REPE/REPZ prefix */
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repnz_present:1, /* REPNE/REPNZ prefix */
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opsize_override:1, /* Operand size override */
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addrsize_override:1, /* Address size override */
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segment_override:1; /* Segment override */
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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int base_register; /* VM_REG_GUEST_xyz */
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int index_register; /* VM_REG_GUEST_xyz */
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int segment_register; /* VM_REG_GUEST_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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struct vie_op op; /* opcode description */
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};
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#define PSL_C 0x00000001U /* carry bit */
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#define PSL_PF 0x00000004U /* parity bit */
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#define PSL_AF 0x00000010U /* bcd carry bit */
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#define PSL_Z 0x00000040U /* zero bit */
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#define PSL_N 0x00000080U /* negative bit */
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#define PSL_T 0x00000100U /* trace enable bit */
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#define PSL_I 0x00000200U /* interrupt enable bit */
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#define PSL_D 0x00000400U /* string instruction direction bit */
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#define PSL_V 0x00000800U /* overflow bit */
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#define PSL_IOPL 0x00003000U /* i/o privilege level */
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#define PSL_NT 0x00004000U /* nested task bit */
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#define PSL_RF 0x00010000U /* resume flag bit */
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#define PSL_VM 0x00020000U /* virtual 8086 mode bit */
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#define PSL_AC 0x00040000U /* alignment checking */
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#define PSL_VIF 0x00080000U /* virtual interrupt enable */
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#define PSL_VIP 0x00100000U /* virtual interrupt pending */
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#define PSL_ID 0x00200000U /* identification bit */
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/*
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* The 'access' field has the format specified in Table 21-2 of the Intel
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* Architecture Manual vol 3b.
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*
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* XXX The contents of the 'access' field are architecturally defined except
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* bit 16 - Segment Unusable.
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*/
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struct seg_desc {
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uint64_t base;
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uint32_t limit;
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uint32_t access;
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};
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/*
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* Protections are chosen from these bits, or-ed together
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*/
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#define PROT_NONE 0x00U /* no permissions */
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#define PROT_READ 0x01U /* pages can be read */
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#define PROT_WRITE 0x02U /* pages can be written */
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#define PROT_EXEC 0x04U /* pages can be executed */
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#define SEG_DESC_TYPE(access) ((access) & 0x001fU)
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#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3U)
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#define SEG_DESC_PRESENT(access) ((((access) & 0x0080U) != 0U) ? 1 : 0)
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#define SEG_DESC_DEF32(access) ((((access) & 0x4000U) != 0U) ? 1 : 0)
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#define SEG_DESC_GRANULARITY(access) ((((access) & 0x8000U) != 0U) ? 1 : 0)
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#define SEG_DESC_UNUSABLE(access) ((((access) & 0x10000U) != 0U) ? 1 : 0)
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struct vm_guest_paging {
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uint64_t cr3;
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int cpl;
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enum vm_cpu_mode cpu_mode;
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enum vm_paging_mode paging_mode;
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};
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struct emul_cnx {
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struct vie vie;
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struct vm_guest_paging paging;
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struct vcpu *vcpu;
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};
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/*
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* Identifiers for architecturally defined registers.
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*/
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enum vm_reg_name {
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VM_REG_GUEST_RAX,
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VM_REG_GUEST_RBX,
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VM_REG_GUEST_RCX,
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VM_REG_GUEST_RDX,
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VM_REG_GUEST_RBP,
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VM_REG_GUEST_RSI,
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VM_REG_GUEST_R8,
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VM_REG_GUEST_R9,
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VM_REG_GUEST_R10,
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VM_REG_GUEST_R11,
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VM_REG_GUEST_R12,
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VM_REG_GUEST_R13,
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VM_REG_GUEST_R14,
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VM_REG_GUEST_R15,
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VM_REG_GUEST_RDI,
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VM_REG_GUEST_CR0,
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VM_REG_GUEST_CR3,
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VM_REG_GUEST_CR4,
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VM_REG_GUEST_DR7,
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VM_REG_GUEST_RSP,
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VM_REG_GUEST_RIP,
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VM_REG_GUEST_RFLAGS,
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VM_REG_GUEST_ES,
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VM_REG_GUEST_CS,
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VM_REG_GUEST_SS,
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VM_REG_GUEST_DS,
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VM_REG_GUEST_FS,
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VM_REG_GUEST_GS,
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VM_REG_GUEST_LDTR,
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VM_REG_GUEST_TR,
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VM_REG_GUEST_IDTR,
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VM_REG_GUEST_GDTR,
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VM_REG_GUEST_EFER,
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VM_REG_GUEST_CR2,
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VM_REG_GUEST_PDPTE0,
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VM_REG_GUEST_PDPTE1,
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VM_REG_GUEST_PDPTE2,
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VM_REG_GUEST_PDPTE3,
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VM_REG_GUEST_INTR_SHADOW,
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VM_REG_LAST
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};
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typedef unsigned long u_long;
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int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval);
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int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val);
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int vm_get_seg_desc(struct vcpu *vcpu, int reg,
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struct seg_desc *ret_desc);
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int vm_set_seg_desc(struct vcpu *vcpu, int reg,
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struct seg_desc *desc);
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#endif
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