Yin Fengwei 5b43521461 hv: trap vm0 write/read pm1a/pm1b registers ... ACRN needs to trap the pm1a/pm1b written/read from VM0. So we could know when should we put the system to S3. We will have two path back to VM0: - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec with real mode - S3 enter/exit failed. Will return to the next instruction of pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt register to check whether it's waked up or not. Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2018-06-29 00:50:01 +08:00
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arch/x86	hv: trap vm0 write/read pm1a/pm1b registers	2018-06-29 00:50:01 +08:00
common	hv: pirq: add a header for common data struct and APIs	2018-06-29 00:50:01 +08:00
debug	hv: prepare for Sx(S3/S5) support in ACRN.	2018-06-29 00:50:01 +08:00
lib	HV: Remove 'register' prefix for data type	2018-06-29 00:50:01 +08:00
public	HV: treewide: enforce unsignedness of pcpu_id	2018-06-21 16:59:21 +08:00
hv_debug.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
hv_lib.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
hypervisor.h	hv: refine the address used in sbl multiboot code	2018-06-22 16:12:24 +08:00