acrn-hypervisor/hypervisor/include/arch/x86/asm
Shiqing Gao 7bbd17ce80 hv: initialize and save/restore IA32_TSC_AUX MSR for guest
Commit cbf3825 "hv: Pass-through IA32_TSC_AUX MSR to L1 guest"
lets guest own the physical MSR IA32_TSC_AUX and does not handle this MSR
in the hypervisor.
If multiple vCPUs share the same pCPU, when one vCPU reads MSR IA32_TSC_AUX,
it may get the value set by other vCPUs.

To fix this issue, this patch does:
 - initialize the MSR content to 0 for the given vCPU, which is consistent with
   the value specified in SDM Vol3 "Table 9-1. IA-32 and Intel 64 Processor
   States Following Power-up, Reset, or INIT"
 - save/restore the MSR content for the given vCPU during context switch

v1 -> v2:
 * According to Table 9-1, the content of IA32_TSC_AUX MSR is unchanged
   following INIT, v2 updates the initialization logic so that the content for
   vCPU is consistent with SDM.

Tracked-On: #6799
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-11-12 09:30:12 +08:00
..
boot hv: remove CONFIG_HV_RAM_SIZE 2021-10-14 15:04:36 +08:00
guest hv: initialize and save/restore IA32_TSC_AUX MSR for guest 2021-11-12 09:30:12 +08:00
lib HV: treewide: fix violations of coding guideline C-TY-12 2021-11-04 18:15:47 +08:00
apicreg.h hv: vlapic: wrap a function to calculate destination vcpu mask by shorthand 2021-05-24 10:27:32 +08:00
board.h
cpu.h hv: initialize and save/restore IA32_TSC_AUX MSR for guest 2021-11-12 09:30:12 +08:00
cpu_caps.h HV: re-use split-lock emulation code for uc-lock 2021-07-21 11:25:47 +08:00
cpufeatures.h
cpuid.h
default_acpi_info.h
e820.h hv: enhance e820_alloc_memory could allocate memory than 4G 2021-10-14 15:04:36 +08:00
gdt.h
host_pm.h hv: dm: Use new power management data structures 2021-07-15 11:53:54 +08:00
idt.h
init.h
io.h
ioapic.h
irq.h hv: dm: Use new I/O request data structures 2021-07-15 11:53:54 +08:00
lapic.h
mmu.h HV: treewide: fix violations of coding guideline C-TY-27 & C-TY-28 2021-11-04 18:15:47 +08:00
msr.h HV: treewide: fix violations of coding guideline C-TY-27 & C-TY-28 2021-11-04 18:15:47 +08:00
notify.h
page.h hv: use per platform maximum physical address width 2021-08-20 11:02:21 +08:00
pci_dev.h
per_cpu.h hv: add priority based scheduler 2021-09-24 09:32:18 +08:00
pgtable.h hv: ivshmem: map SHM BAR with PAT ignored 2021-08-13 11:17:15 +08:00
platform_caps.h
rdt.h hv: vCAT: initialize vCAT MSRs during vmcs init 2021-10-28 19:12:29 +08:00
rtcm.h hv: update RTCT ACPI table detecting 2021-06-01 08:22:20 +08:00
rtct.h HV: refine the ve820 tab for pre-VMs 2021-11-08 13:13:14 +08:00
security.h
seed.h
sgx.h
trampoline.h
tsc.h doc: update timer HLD doc after modularization 2021-06-09 17:11:25 -04:00
vm_config.h ACRN: misc: Unify terminology for service vm/user vm 2021-11-02 10:00:55 +08:00
vmx.h hv: Use 64 bits definition for 64 bits MSR_IA32_VMX_EPT_VPID_CAP operation 2021-07-02 09:24:12 +08:00
vtd.h HV: treewide: fix violations of coding guideline C-PP-04 2021-11-04 18:15:47 +08:00
zeropage.h HV: place kernel and ramdisk by find_space_from_ve820() 2021-06-11 10:06:02 +08:00