acrn-hypervisor/hypervisor/include
Shiqing Gao 7bbd17ce80 hv: initialize and save/restore IA32_TSC_AUX MSR for guest
Commit cbf3825 "hv: Pass-through IA32_TSC_AUX MSR to L1 guest"
lets guest own the physical MSR IA32_TSC_AUX and does not handle this MSR
in the hypervisor.
If multiple vCPUs share the same pCPU, when one vCPU reads MSR IA32_TSC_AUX,
it may get the value set by other vCPUs.

To fix this issue, this patch does:
 - initialize the MSR content to 0 for the given vCPU, which is consistent with
   the value specified in SDM Vol3 "Table 9-1. IA-32 and Intel 64 Processor
   States Following Power-up, Reset, or INIT"
 - save/restore the MSR content for the given vCPU during context switch

v1 -> v2:
 * According to Table 9-1, the content of IA32_TSC_AUX MSR is unchanged
   following INIT, v2 updates the initialization logic so that the content for
   vCPU is consistent with SDM.

Tracked-On: #6799
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-11-12 09:30:12 +08:00
..
arch/x86/asm hv: initialize and save/restore IA32_TSC_AUX MSR for guest 2021-11-12 09:30:12 +08:00
common HV: move the ve820 GPU OpRegion address 2021-11-08 13:13:14 +08:00
debug hv: debug: Add hv console callback to VM-exit event 2021-07-22 10:08:23 +08:00
dm HV: move the ve820 GPU OpRegion address 2021-11-08 13:13:14 +08:00
hw HV: treewide: fix violations of coding guideline C-TY-02 2021-11-04 18:15:47 +08:00
lib HV: treewide: fix violations of coding guideline C-PP-04 2021-11-04 18:15:47 +08:00
public HV: treewide: fix violations of coding guideline C-TY-12 2021-11-04 18:15:47 +08:00