426 lines
11 KiB
C
426 lines
11 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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/*
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* WatchDog Timer (WDT): emulate i6300esb PCI wdt Intel SOC devices,
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* used to monitor guest OS
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdbool.h>
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#include "vmmapi.h"
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#include "mevent.h"
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#include "pci_core.h"
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#include "timer.h"
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#define WDT_REG_BAR_SIZE 0x10
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ESB 0x25ab
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#define ESB_CONFIG_REG 0x60 /* Config register*/
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#define ESB_LOCK_REG 0x68 /* WDT lock register*/
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/* Memory mapped registers */
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#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
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#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
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#define ESB_GIS_REG 0x08 /* General Interrupt Status register */
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#define ESB_RELOAD_REG 0x0c /* Reload register */
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#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
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#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
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#define ESB_WDT_INT_ACT (0x01 << 0) /* WDT INT is active */
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#define ESB_WDT_INT_MSK 0x3 /* WDT INT TYPE mask */
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#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
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#define ESB_WDT_RELOAD (0x01 << 8) /* Ping/kick dog */
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#define ESB_WDT_TIMEOUT (0x01 << 9) /* WDT timeout happened? */
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/* Per i6300esb spec, in default watchdog timer prescaler
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* the 20-bit Preload Value is loaded into bits 34:15 of the
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* main down counter. The resulting timer clock is the PCI
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* Clock (33 MHz) divided by 2^^15 . The approximate clock
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* generated is 1 KHz, so right shift 10 bits of preload value
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* to get the exact seconds for this timer.
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*/
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#define TIMER_TO_SECONDS(val) (val >> 10)
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/* Magic constants */
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#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
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#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
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/* the default 20-bit preload value */
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#define DEFAULT_MAX_TIMER_VAL 0x000FFFFF
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/* stage timer is set to 60s after reset, then left shift 10 bits of seconds
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* to transform to the preload value of the watchdog timer which run in
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* 1KHz clock.
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*/
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#define DEFAULT_RESET_TIMER_VAL (60 << 10)
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/* for debug */
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/* #define WDT_DEBUG */
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#ifdef WDT_DEBUG
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static FILE * dbg_file;
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#define DPRINTF(format, args...) \
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do { fprintf(dbg_file, format, args); fflush(dbg_file); } while (0)
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#else
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#define DPRINTF(format, arg...)
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#endif
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struct info_wdt {
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struct acrn_timer timer;
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bool reboot_enabled;/* "reboot" on wdt out */
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bool intr_enabled; /* "intr" on wdt stage 1 time out */
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bool intr_active; /* interrupt is active */
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bool locked; /* If true, enabled field cannot be changed. */
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bool wdt_enabled; /* If true, watchdog is enabled. */
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bool wdt_armed;
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uint32_t timer1_val;
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uint32_t timer2_val;
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int stage; /* stage 1 or 2. */
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int unlock_state; /* unlock states 0 -> 1 -> 2 */
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};
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/* Whether watchdog is timeout. This info should cross reset. So
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* we didn't add to struct info_wdt.
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*/
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static int wdt_timeout = 0;
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static struct info_wdt wdt_state;
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static void start_wdt_timer(void);
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/*
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* WDT timer, start when guest OS start watchdog service; and re-start for
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* each dog-kick / ping action if time out, it will trigger reboot or other
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* action to guest OS
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*/
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static void
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wdt_expired_handler(void *arg, uint64_t nexp)
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{
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struct pci_vdev *dev = (struct pci_vdev *)arg;
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DPRINTF("wdt timer out! stage=%d, reboot=%d\n",
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wdt_state.stage, wdt_state.reboot_enabled);
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if (wdt_state.stage == 1) {
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if (wdt_state.intr_enabled) {
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if (pci_msi_enabled(dev))
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pci_generate_msi(dev, 0);
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else
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pci_lintr_assert(dev);
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wdt_state.intr_active = true;
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}
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wdt_state.stage = 2;
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start_wdt_timer();
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} else {
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if (wdt_state.reboot_enabled) {
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wdt_state.stage = 1;
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wdt_timeout = 1;
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/* watchdog timer out, set the uos to reboot */
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#ifdef DM_DEBUG
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pr_info("%s: setting VM state to %s\n", __func__, vm_state_to_str(VM_SUSPEND_SYSTEM_RESET));
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vm_set_suspend_mode(VM_SUSPEND_SYSTEM_RESET);
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/* Notify vm thread to handle VM_SUSPEND_SYSTEM_RESET request */
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notify_vmloop_thread();
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#else
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pr_info("%s: setting VM state to %s\n", __func__, vm_state_to_str(VM_SUSPEND_FULL_RESET));
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vm_set_suspend_mode(VM_SUSPEND_FULL_RESET);
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#endif
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mevent_notify();
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} else {
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/* if not need reboot, just loop timer */
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wdt_state.stage = 1;
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start_wdt_timer();
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}
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}
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}
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static void
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stop_wdt_timer(void)
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{
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struct itimerspec timer_val;
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DPRINTF("%s: wdt_armed=%d\n", __func__, wdt_state.wdt_armed);
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if (!wdt_state.wdt_armed)
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return;
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memset(&timer_val, 0, sizeof(struct itimerspec));
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acrn_timer_settime(&wdt_state.timer, &timer_val);
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wdt_state.wdt_armed = false;
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}
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static void
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start_wdt_timer(void)
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{
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int seconds;
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struct itimerspec timer_val;
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if (!wdt_state.wdt_enabled)
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return;
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if (wdt_state.stage == 1)
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seconds = TIMER_TO_SECONDS(wdt_state.timer1_val);
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else
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seconds = TIMER_TO_SECONDS(wdt_state.timer2_val);
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DPRINTF("%s: armed=%d, time=%d\n", __func__,
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wdt_state.wdt_armed, seconds);
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memset(&timer_val, 0, sizeof(struct itimerspec));
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timer_val.it_value.tv_sec = seconds;
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if (acrn_timer_settime(&wdt_state.timer, &timer_val) == -1) {
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pr_err("WDT timerfd_settime failed.\n");
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wdt_state.wdt_armed = false;
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return;
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}
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wdt_state.wdt_armed = true;
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}
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static int
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pci_wdt_cfg_read(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
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int offset, int bytes, uint32_t *rv)
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{
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int need_cfg = 1;
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DPRINTF("%s: offset = %x, len = %d\n", __func__, offset, bytes);
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if (offset == ESB_LOCK_REG && bytes == 1) {
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*rv = (wdt_state.locked ? ESB_WDT_LOCK : 0) |
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(wdt_state.wdt_enabled ? ESB_WDT_ENABLE : 0);
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need_cfg = 0;
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}
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return need_cfg;
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}
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static int
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pci_wdt_cfg_write(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
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int offset, int bytes, uint32_t val)
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{
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bool old_flag;
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int need_cfg = 1;
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DPRINTF("%s: offset = %x, len = %d, val = 0x%x\n",
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__func__, offset, bytes, val);
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if (offset == ESB_CONFIG_REG && bytes == 2) {
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wdt_state.reboot_enabled = ((val & ESB_WDT_REBOOT) == 0);
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wdt_state.intr_enabled = ((val & ESB_WDT_INT_MSK) == 0);
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need_cfg = 0;
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} else if (offset == ESB_LOCK_REG && bytes == 1) {
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if (!wdt_state.locked) {
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wdt_state.locked = ((val & ESB_WDT_LOCK) != 0);
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old_flag = wdt_state.wdt_enabled;
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wdt_state.wdt_enabled = ((val & ESB_WDT_ENABLE) != 0);
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if (!old_flag && wdt_state.wdt_enabled) {
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wdt_state.stage = 1;
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start_wdt_timer();
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} else if (!wdt_state.wdt_enabled)
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stop_wdt_timer();
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}
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need_cfg = 0;
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}
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return need_cfg;
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}
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static void
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pci_wdt_bar_write(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
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int baridx, uint64_t offset, int size, uint64_t value)
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{
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DPRINTF("%s: addr = 0x%x, val = 0x%x, size=%d\n",
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__func__, (int) offset, (int)value, size);
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if (offset == ESB_GIS_REG) {
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if ((value & ESB_WDT_INT_ACT) == 1) {
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wdt_state.intr_active = false;
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if ((wdt_state.intr_enabled == true)
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&& (dev->lintr.state == ASSERTED)) {
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pci_lintr_deassert(dev);
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DPRINTF("%s: intr deasserted\n\r", __func__);
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}
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}
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} else if (offset == ESB_RELOAD_REG) {
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if (size != 2)
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return;
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if (value == ESB_UNLOCK1)
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wdt_state.unlock_state = 1;
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else if ((value == ESB_UNLOCK2)
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&& (wdt_state.unlock_state == 1))
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wdt_state.unlock_state = 2;
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else if (wdt_state.unlock_state == 2) {
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if (value & ESB_WDT_RELOAD) {
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wdt_state.stage = 1;
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start_wdt_timer();
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}
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/* write ES_WDT_TIMEOUT bit clear wdt timeout */
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if (value & ESB_WDT_TIMEOUT) {
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DPRINTF("%s: timeout cleaned\n\r", __func__);
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wdt_timeout = 0;
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}
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wdt_state.unlock_state = 0;
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}
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} else if (wdt_state.unlock_state == 2) {
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if (offset == ESB_TIMER1_REG)
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wdt_state.timer1_val = value & DEFAULT_MAX_TIMER_VAL;
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else if (offset == ESB_TIMER2_REG)
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wdt_state.timer2_val = value & DEFAULT_MAX_TIMER_VAL;
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wdt_state.unlock_state = 0;
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}
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}
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uint64_t
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pci_wdt_bar_read(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
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int baridx, uint64_t offset, int size)
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{
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uint64_t ret = 0;
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DPRINTF("%s: addr = 0x%x, size=%d\n\r", __func__, (int) offset, size);
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if (offset == ESB_GIS_REG) {
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if ((wdt_state.intr_enabled == true)
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&& (wdt_state.intr_active == true))
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ret |= ESB_WDT_INT_ACT;
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} else if (offset == ESB_RELOAD_REG) {
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if (size != 2)
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return 0;
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DPRINTF("%s: timeout: %d\n\r", __func__, wdt_timeout);
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if (wdt_timeout != 0)
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ret |= ESB_WDT_TIMEOUT;
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if (wdt_state.stage == 1)
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ret |= ESB_WDT_RELOAD;
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}
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return ret;
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}
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static int
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pci_wdt_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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/*the wdt just has one inistance */
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if (wdt_state.reboot_enabled && wdt_state.timer1_val) {
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pr_err("wdt can't be initialized twice, please check!");
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return -1;
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}
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/* init wdt state info */
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wdt_state.timer.clockid = CLOCK_MONOTONIC;
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if (acrn_timer_init(&wdt_state.timer, wdt_expired_handler, dev) != 0) {
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return -1;
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}
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wdt_state.reboot_enabled = true;
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wdt_state.intr_enabled = false;
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wdt_state.intr_active = false;
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wdt_state.locked = false;
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wdt_state.wdt_armed = false;
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wdt_state.wdt_enabled = false;
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wdt_state.stage = 1;
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wdt_state.timer1_val = DEFAULT_MAX_TIMER_VAL;
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wdt_state.timer2_val = DEFAULT_MAX_TIMER_VAL;
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wdt_state.unlock_state = 0;
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pci_emul_alloc_bar(dev, 0, PCIBAR_MEM32, WDT_REG_BAR_SIZE);
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/* initialize config space */
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pci_set_cfgdata16(dev, PCIR_VENDOR, PCI_VENDOR_ID_INTEL);
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pci_set_cfgdata16(dev, PCIR_DEVICE, PCI_DEVICE_ID_INTEL_ESB);
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pci_set_cfgdata8(dev, PCIR_CLASS, PCIC_BASEPERIPH);
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pci_set_cfgdata8(dev, PCIR_SUBCLASS, PCIS_BASEPERIPH_OTHER);
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pci_emul_add_msicap(dev, 1);
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pci_lintr_request(dev);
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#ifdef WDT_DEBUG
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dbg_file = fopen("/tmp/wdt_log", "w+");
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#endif
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DPRINTF("%s: iobar =0x%lx, size=%ld\n", __func__,
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dev->bar[0].addr, dev->bar[0].size);
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return 0;
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}
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static void
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pci_wdt_deinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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acrn_timer_deinit(&wdt_state.timer);
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memset(&wdt_state, 0, sizeof(wdt_state));
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pci_lintr_release(dev);
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}
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/* stop/reset watchdog will be invoked during guest enter/exit S3.
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* We stop watchdog timer when guest enter S3 to avoid watchdog trigger
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* guest reset when guest is in S3 state.
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*
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* We reset watchdog with a long peroid (2 * 60s) during guest exit
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* from S3 to handle system hang before watchdog in guest kernel start to
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* work.
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*/
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void
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vm_stop_watchdog(struct vmctx *ctx)
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{
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stop_wdt_timer();
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}
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void
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vm_reset_watchdog(struct vmctx *ctx)
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{
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wdt_state.stage = 1;
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wdt_state.timer1_val = DEFAULT_RESET_TIMER_VAL;
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wdt_state.timer2_val = DEFAULT_RESET_TIMER_VAL;
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wdt_state.unlock_state = 0;
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start_wdt_timer();
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}
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struct pci_vdev_ops pci_ops_wdt = {
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.class_name = "wdt-i6300esb",
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.vdev_init = pci_wdt_init,
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.vdev_deinit = pci_wdt_deinit,
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.vdev_cfgwrite = pci_wdt_cfg_write,
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.vdev_cfgread = pci_wdt_cfg_read,
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.vdev_barwrite = pci_wdt_bar_write,
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.vdev_barread = pci_wdt_bar_read
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};
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DEFINE_PCI_DEVTYPE(pci_ops_wdt);
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