add logs for vm state transition to help
analyze some problems.
Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
use acrn-dm logger function instread of perror,
this helps the stability testing log capture.
Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
cleanup 'assert' usage to avoid possible software vulnerabilities
Tracked-On: #3252
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Per debugging requirement, map the watchdog reset to warm reset.
So the ramconsole could be used to capture the kernel log of UOS
before watchdog is hit.
Tracked-On: #2471
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
It is possible for multiple timeouts to occur in one mevent epoll
iteration. Providing the number of timer expirations to the timer
callback handlers can be useful. E.g., this could improve emulation of
timing-sensitive hardware components.
Tracked-On: #2319
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Per i6300esb spec, when WDT_INT_TYPE(bit 0 and 1 of WDT config register)
are set to 00, IRQ feature should be supported.
The WDT_INT_ACTIVE bit is set when the first stage of the 35-bit
down-counter reaches zero. An interrupt will be generated if WDT_INT_TYPE
is configured to do so (See WDT Configuration Register). This is a sticky
bit and is only cleared by writing a 1.
SMI feature(WDT_INT_TYPE are set to 0x10) is not supported.
Tracked-On: #1498
Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
In the current implementation sigev_notify is configured as
SIGEV_THREAD. When wdt expires an async thread is created and
the registered timer callback is called in the context of this
thread, then the watchdog interrupt emulation would require the
thread to assert intr on this pci dev.
There would be a race condition that when the wdt pci device is
freed in pci device deinit and then a timer expires. In this case
the wdt expired thread will access a freed buffer which would cause
problem such as heap corruption and segment fault.
In this patch we replace timer API with acrn_timer which is based
on timerfd/epoll mechanism to avoid the race condition.
Tracked-On: #1489
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
1. In default prescaler, the wdt clock is 1 KHz for a 20-bit counter,
which means approximate 1 second for 10 bits;
2. the default reset timer in seconds need to left shift 10 bits to
represent the value that set to i6300esb register;
Tracked-On: #1142
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
When guest enter/exit S3, we need to do
1. stop watchdog timer when guest enter S3 to avoid watchdog
timer reset guest when guest is in S3 state.
2. reset watchdog timer when guest exit from S3.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Guest has erquirement to support system/full reboot and S3. Which could
trigger different reset path in guest
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
6300esb has bit in its register to show whether the watchdog
timeout is hit.
This patch adds this bit support. So the guest could query
whether last reset is triggered by watchdog reset.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Cao Minggui <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Tested-by: Binbin Wu <binbin.wu@intel.com>
to avoid system resource/memory leaked when guest os reboot.
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Mingqiang Chi