555 lines
28 KiB
C
555 lines
28 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MSR_H
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#define MSR_H
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/* architectural (common) MSRs */
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#define MSR_IA32_P5_MC_ADDR 0x00000000
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/* Machine check address for MC exception handler */
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#define MSR_IA32_P5_MC_TYPE 0x00000001
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/* Machine check error type for MC exception handler */
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#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
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/* System coherence line size for MWAIT/MONITOR */
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#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010 /* TSC as MSR */
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#define MSR_IA32_PLATFORM_ID 0x00000017 /* Platform ID */
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#define MSR_IA32_APIC_BASE 0x0000001B
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/* Information about LAPIC */
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#define MSR_IA32_FEATURE_CONTROL 0x0000003A
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/* Speculation Control */
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#define MSR_IA32_SPEC_CTRL 0x00000048
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/* Prediction Command */
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#define MSR_IA32_PRED_CMD 0x00000049
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/* Control Features in Intel 64 processor */
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#define MSR_IA32_ADJUST_TSC 0x0000003B /* Adjust TSC value */
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#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
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/* BIOS update trigger */
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#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
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/* BIOS update signature */
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#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
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/* SMM monitor configuration */
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#define MSR_IA32_PMC0 0x000000C1
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/* General performance counter 0 */
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#define MSR_IA32_PMC1 0x000000C2
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/* General performance counter 1 */
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#define MSR_IA32_PMC2 0x000000C3
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/* General performance counter 2 */
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#define MSR_IA32_PMC3 0x000000C4
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/* General performance counter 3 */
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#define MSR_IA32_MPERF 0x000000E7
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/* Max. qualified performance clock counter */
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#define MSR_IA32_APERF 0x000000E8
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/* Actual performance clock counter */
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#define MSR_IA32_MTRR_CAP 0x000000FE /* MTRR capability */
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#define MSR_IA32_SYSENTER_CS 0x00000174 /* CS for sysenter */
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#define MSR_IA32_SYSENTER_ESP 0x00000175 /* ESP for sysenter */
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#define MSR_IA32_SYSENTER_EIP 0x00000176 /* EIP for sysenter */
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#define MSR_IA32_MCG_CAP 0x00000179
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/* Global machine check capability */
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#define MSR_IA32_MCG_STATUS 0x0000017A
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/* Global machine check status */
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#define MSR_IA32_MCG_CTL 0x0000017B
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/* Global machine check control */
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#define MSR_IA32_PERFEVTSEL0 0x00000186
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/* Performance Event Select Register 0 */
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#define MSR_IA32_PERFEVTSEL1 0x00000187
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/* Performance Event Select Register 1 */
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#define MSR_IA32_PERFEVTSEL2 0x00000188
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/* Performance Event Select Register 2 */
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#define MSR_IA32_PERFEVTSEL3 0x00000189
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/* Performance Event Select Register 3 */
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#define MSR_IA32_PERF_STATUS 0x00000198
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/* Current performance state */
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#define MSR_IA32_PERF_CTL 0x00000199
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/* Performance control */
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#define MSR_IA32_CLOCK_MODULATION 0x0000019A
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/* Clock modulation control */
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#define MSR_IA32_THERM_INTERRUPT 0x0000019B
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/* Thermal interrupt control */
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#define MSR_IA32_THERM_STATUS 0x0000019C
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/* Thermal status information */
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#define MSR_IA32_MISC_ENABLE 0x000001A0
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/* Enable misc. processor features */
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
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/* Performance energy bias hint */
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#define MSR_IA32_DEBUGCTL 0x000001D9
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/* Trace/Profile resource control */
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#define MSR_IA32_SMRR_PHYSBASE 0x000001F2 /* SMRR base address */
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#define MSR_IA32_SMRR_PHYSMASK 0x000001F3 /* SMRR range mask */
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#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 /* DCA capability */
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#define MSR_IA32_CPU_DCA_CAP 0x000001F9
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/* Prefetch hint type capability */
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#define MSR_IA32_DCA_0_CAP 0x000001FA
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/* DCA type 0 status/control */
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#define MSR_IA32_MTRR_PHYSBASE_0 0x00000200
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/* variable range MTRR base 0 */
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#define MSR_IA32_MTRR_PHYSMASK_0 0x00000201
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/* variable range MTRR mask 0 */
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#define MSR_IA32_MTRR_PHYSBASE_1 0x00000202
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/* variable range MTRR base 1 */
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#define MSR_IA32_MTRR_PHYSMASK_1 0x00000203
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/* variable range MTRR mask 1 */
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#define MSR_IA32_MTRR_PHYSBASE_2 0x00000204
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/* variable range MTRR base 2 */
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#define MSR_IA32_MTRR_PHYSMASK_2 0x00000205
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/* variable range MTRR mask 2 */
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#define MSR_IA32_MTRR_PHYSBASE_3 0x00000206
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/* variable range MTRR base 3 */
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#define MSR_IA32_MTRR_PHYSMASK_3 0x00000207
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/* variable range MTRR mask 3 */
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#define MSR_IA32_MTRR_PHYSBASE_4 0x00000208
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/* variable range MTRR base 4 */
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#define MSR_IA32_MTRR_PHYSMASK_4 0x00000209
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/* variable range MTRR mask 4 */
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#define MSR_IA32_MTRR_PHYSBASE_5 0x0000020A
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/* variable range MTRR base 5 */
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#define MSR_IA32_MTRR_PHYSMASK_5 0x0000020B
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/* variable range MTRR mask 5 */
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#define MSR_IA32_MTRR_PHYSBASE_6 0x0000020C
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/* variable range MTRR base 6 */
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#define MSR_IA32_MTRR_PHYSMASK_6 0x0000020D
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/* variable range MTRR mask 6 */
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#define MSR_IA32_MTRR_PHYSBASE_7 0x0000020E
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/* variable range MTRR base 7 */
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#define MSR_IA32_MTRR_PHYSMASK_7 0x0000020F
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/* variable range MTRR mask 7 */
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#define MSR_IA32_MTRR_PHYSBASE_8 0x00000210
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/* variable range MTRR base 8 */
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#define MSR_IA32_MTRR_PHYSMASK_8 0x00000211
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/* variable range MTRR mask 8 */
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#define MSR_IA32_MTRR_PHYSBASE_9 0x00000212
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/* variable range MTRR base 9 */
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#define MSR_IA32_MTRR_PHYSMASK_9 0x00000213
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/* variable range MTRR mask 9 */
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#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
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/* fixed range MTRR 16K/0x00000 */
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#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
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/* fixed range MTRR 16K/0x80000 */
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#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
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/* fixed range MTRR 16K/0xA0000 */
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#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
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/* fixed range MTRR 4K/0xC0000 */
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#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
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/* fixed range MTRR 4K/0xC8000 */
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#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
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/* fixed range MTRR 4K/0xD0000 */
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#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
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/* fixed range MTRR 4K/0xD8000 */
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#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
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/* fixed range MTRR 4K/0xE0000 */
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#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
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/* fixed range MTRR 4K/0xE8000 */
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#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
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/* fixed range MTRR 4K/0xF0000 */
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#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
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/* fixed range MTRR 4K/0xF8000 */
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#define MSR_IA32_PAT 0x00000277 /* PAT */
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#define MSR_IA32_MC0_CTL2 0x00000280
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/* Corrected error count threshold 0 */
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#define MSR_IA32_MC1_CTL2 0x00000281
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/* Corrected error count threshold 1 */
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#define MSR_IA32_MC2_CTL2 0x00000282
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/* Corrected error count threshold 2 */
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#define MSR_IA32_MC3_CTL2 0x00000283
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/* Corrected error count threshold 3 */
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#define MSR_IA32_MC4_CTL2 0x00000284
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/* Corrected error count threshold 4 */
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#define MSR_IA32_MC5_CTL2 0x00000285
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/* Corrected error count threshold 5 */
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#define MSR_IA32_MC6_CTL2 0x00000286
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/* Corrected error count threshold 6 */
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#define MSR_IA32_MC7_CTL2 0x00000287
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/* Corrected error count threshold 7 */
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#define MSR_IA32_MC8_CTL2 0x00000288
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/* Corrected error count threshold 8 */
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#define MSR_IA32_MC9_CTL2 0x00000289
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/* Corrected error count threshold 9 */
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#define MSR_IA32_MC10_CTL2 0x0000028A
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/* Corrected error count threshold 10 */
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#define MSR_IA32_MC11_CTL2 0x0000028B
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/* Corrected error count threshold 11 */
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#define MSR_IA32_MC12_CTL2 0x0000028C
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/* Corrected error count threshold 12 */
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#define MSR_IA32_MC13_CTL2 0x0000028D
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/* Corrected error count threshold 13 */
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#define MSR_IA32_MC14_CTL2 0x0000028E
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/* Corrected error count threshold 14 */
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#define MSR_IA32_MC15_CTL2 0x0000028F
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/* Corrected error count threshold 15 */
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#define MSR_IA32_MC16_CTL2 0x00000290
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/* Corrected error count threshold 16 */
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#define MSR_IA32_MC17_CTL2 0x00000291
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/* Corrected error count threshold 17 */
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#define MSR_IA32_MC18_CTL2 0x00000292
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/* Corrected error count threshold 18 */
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#define MSR_IA32_MC19_CTL2 0x00000293
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/* Corrected error count threshold 19 */
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#define MSR_IA32_MC20_CTL2 0x00000294
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/* Corrected error count threshold 20 */
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#define MSR_IA32_MC21_CTL2 0x00000295
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/* Corrected error count threshold 21 */
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#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
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/* Default memory type/MTRR control */
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#define MSR_IA32_FIXED_CTR0 0x00000309
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/* Fixed-function performance counter 0 */
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#define MSR_IA32_FIXED_CTR1 0x0000030A
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/* Fixed-function performance counter 1 */
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#define MSR_IA32_FIXED_CTR2 0x0000030B
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/* Fixed-function performance counter 2 */
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345
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/* Performance capability */
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#define MSR_IA32_FIXED_CTR_CTL 0x0000038D
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/* Fixed-function performance counter control */
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#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
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/* Global performance counter status */
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#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
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/* Global performance counter control */
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#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
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/* Global performance counter overflow control */
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#define MSR_IA32_PEBS_ENABLE 0x000003F1 /* PEBS control */
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#define MSR_IA32_MC0_CTL 0x00000400 /* MC 0 control */
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#define MSR_IA32_MC0_STATUS 0x00000401 /* MC 0 status */
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#define MSR_IA32_MC0_ADDR 0x00000402 /* MC 0 address */
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#define MSR_IA32_MC0_MISC 0x00000403 /* MC 0 misc. */
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#define MSR_IA32_MC1_CTL 0x00000404 /* MC 1 control */
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#define MSR_IA32_MC1_STATUS 0x00000405 /* MC 1 status */
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#define MSR_IA32_MC1_ADDR 0x00000406 /* MC 1 address */
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#define MSR_IA32_MC1_MISC 0x00000407 /* MC 1 misc. */
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#define MSR_IA32_MC2_CTL 0x00000408 /* MC 2 control */
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#define MSR_IA32_MC2_STATUS 0x00000409 /* MC 2 status */
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#define MSR_IA32_MC2_ADDR 0x0000040A /* MC 2 address */
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#define MSR_IA32_MC2_MISC 0x0000040B /* MC 2 misc. */
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#define MSR_IA32_MC3_CTL 0x0000040C /* MC 3 control */
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#define MSR_IA32_MC3_STATUS 0x0000040D /* MC 3 status */
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#define MSR_IA32_MC3_ADDR 0x0000040E /* MC 3 address */
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#define MSR_IA32_MC3_MISC 0x0000040F /* MC 3 misc. */
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#define MSR_IA32_MC4_CTL 0x00000410 /* MC 4 control */
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#define MSR_IA32_MC4_STATUS 0x00000411 /* MC 4 status */
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#define MSR_IA32_MC4_ADDR 0x00000412 /* MC 4 address */
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#define MSR_IA32_MC4_MISC 0x00000413 /* MC 4 misc. */
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#define MSR_IA32_MC5_CTL 0x00000414 /* MC 5 control */
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#define MSR_IA32_MC5_STATUS 0x00000415 /* MC 5 status */
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#define MSR_IA32_MC5_ADDR 0x00000416 /* MC 5 address */
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#define MSR_IA32_MC5_MISC 0x00000417 /* MC 5 misc. */
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#define MSR_IA32_MC6_CTL 0x00000418 /* MC 6 control */
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#define MSR_IA32_MC6_STATUS 0x00000419 /* MC 6 status */
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#define MSR_IA32_MC6_ADDR 0x0000041A /* MC 6 address */
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#define MSR_IA32_MC6_MISC 0x0000041B /* MC 6 misc. */
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#define MSR_IA32_MC7_CTL 0x0000041C /* MC 7 control */
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#define MSR_IA32_MC7_STATUS 0x0000041D /* MC 7 status */
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#define MSR_IA32_MC7_ADDR 0x0000041E /* MC 7 address */
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#define MSR_IA32_MC7_MISC 0x0000041F /* MC 7 misc. */
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#define MSR_IA32_MC8_CTL 0x00000420 /* MC 8 control */
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#define MSR_IA32_MC8_STATUS 0x00000421 /* MC 8 status */
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#define MSR_IA32_MC8_ADDR 0x00000422 /* MC 8 address */
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#define MSR_IA32_MC8_MISC 0x00000423 /* MC 8 misc. */
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#define MSR_IA32_MC9_CTL 0x00000424 /* MC 9 control */
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#define MSR_IA32_MC9_STATUS 0x00000425 /* MC 9 status */
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#define MSR_IA32_MC9_ADDR 0x00000426 /* MC 9 address */
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#define MSR_IA32_MC9_MISC 0x00000427 /* MC 9 misc. */
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#define MSR_IA32_MC10_CTL 0x00000428 /* MC 10 control */
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#define MSR_IA32_MC10_STATUS 0x00000429 /* MC 10 status */
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#define MSR_IA32_MC10_ADDR 0x0000042A /* MC 10 address */
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#define MSR_IA32_MC10_MISC 0x0000042B /* MC 10 misc. */
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#define MSR_IA32_MC11_CTL 0x0000042C /* MC 11 control */
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#define MSR_IA32_MC11_STATUS 0x0000042D /* MC 11 status */
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#define MSR_IA32_MC11_ADDR 0x0000042E /* MC 11 address */
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#define MSR_IA32_MC11_MISC 0x0000042F /* MC 11 misc. */
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#define MSR_IA32_MC12_CTL 0x00000430 /* MC 12 control */
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#define MSR_IA32_MC12_STATUS 0x00000431 /* MC 12 status */
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#define MSR_IA32_MC12_ADDR 0x00000432 /* MC 12 address */
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#define MSR_IA32_MC12_MISC 0x00000433 /* MC 12 misc. */
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#define MSR_IA32_MC13_CTL 0x00000434 /* MC 13 control */
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#define MSR_IA32_MC13_STATUS 0x00000435 /* MC 13 status */
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#define MSR_IA32_MC13_ADDR 0x00000436 /* MC 13 address */
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#define MSR_IA32_MC13_MISC 0x00000437 /* MC 13 misc. */
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#define MSR_IA32_MC14_CTL 0x00000438 /* MC 14 control */
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#define MSR_IA32_MC14_STATUS 0x00000439 /* MC 14 status */
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#define MSR_IA32_MC14_ADDR 0x0000043A /* MC 14 address */
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#define MSR_IA32_MC14_MISC 0x0000043B /* MC 14 misc. */
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#define MSR_IA32_MC15_CTL 0x0000043C /* MC 15 control */
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#define MSR_IA32_MC15_STATUS 0x0000043D /* MC 15 status */
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#define MSR_IA32_MC15_ADDR 0x0000043E /* MC 15 address */
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#define MSR_IA32_MC15_MISC 0x0000043F /* MC 15 misc. */
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#define MSR_IA32_MC16_CTL 0x00000440 /* MC 16 control */
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#define MSR_IA32_MC16_STATUS 0x00000441 /* MC 16 status */
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#define MSR_IA32_MC16_ADDR 0x00000442 /* MC 16 address */
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#define MSR_IA32_MC16_MISC 0x00000443 /* MC 16 misc. */
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#define MSR_IA32_MC17_CTL 0x00000444 /* MC 17 control */
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#define MSR_IA32_MC17_STATUS 0x00000445 /* MC 17 status */
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#define MSR_IA32_MC17_ADDR 0x00000446 /* MC 17 address */
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#define MSR_IA32_MC17_MISC 0x00000447 /* MC 17 misc. */
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#define MSR_IA32_MC18_CTL 0x00000448 /* MC 18 control */
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#define MSR_IA32_MC18_STATUS 0x00000449 /* MC 18 status */
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#define MSR_IA32_MC18_ADDR 0x0000044A /* MC 18 address */
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#define MSR_IA32_MC18_MISC 0x0000044B /* MC 18 misc. */
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#define MSR_IA32_MC19_CTL 0x0000044C /* MC 19 control */
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#define MSR_IA32_MC19_STATUS 0x0000044D /* MC 19 status */
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#define MSR_IA32_MC19_ADDR 0x0000044E /* MC 19 address */
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#define MSR_IA32_MC19_MISC 0x0000044F /* MC 19 misc. */
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#define MSR_IA32_MC20_CTL 0x00000450 /* MC 20 control */
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#define MSR_IA32_MC20_STATUS 0x00000451 /* MC 20 status */
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#define MSR_IA32_MC20_ADDR 0x00000452 /* MC 20 address */
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#define MSR_IA32_MC20_MISC 0x00000453 /* MC 20 misc. */
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#define MSR_IA32_MC21_CTL 0x00000454 /* MC 21 control */
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#define MSR_IA32_MC21_STATUS 0x00000455 /* MC 21 status */
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#define MSR_IA32_MC21_ADDR 0x00000456 /* MC 21 address */
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#define MSR_IA32_MC21_MISC 0x00000457 /* MC 21 misc. */
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#define MSR_IA32_VMX_BASIC 0x00000480
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/* Capability reporting register basic VMX capabilities */
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#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
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/* Capability reporting register pin based VM execution controls */
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#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
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/* Capability reporting register primary processor based VM execution controls*/
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#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
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/* Capability reporting register VM exit controls */
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#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
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/* Capability reporting register VM entry controls */
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#define MSR_IA32_VMX_MISC 0x00000485
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/* Reporting register misc. VMX capabilities */
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#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
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/* Capability reporting register of CR0 bits fixed to 0 */
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#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
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/* Capability reporting register of CR0 bits fixed to 1 */
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#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
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/* Capability reporting register of CR4 bits fixed to 0 */
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#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
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/* Capability reporting register of CR4 bits fixed to 1 */
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#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
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/* Capability reporting register of VMCS field enumeration */
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#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
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/* Capability reporting register of secondary processor based VM execution
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* controls
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*/
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#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
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/* Capability reporting register of EPT and VPID */
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#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
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/* Capability reporting register of pin based VM execution flex controls */
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#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
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/* Capability reporting register of primary processor based VM execution flex
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* controls
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*/
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#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
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/* Capability reporting register of VM exit flex controls */
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#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
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/* Capability reporting register of VM entry flex controls */
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#define MSR_IA32_DS_AREA 0x00000600 /* DS save area */
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/* APIC TSC deadline MSR */
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#define MSR_IA32_TSC_DEADLINE 0x000006E0
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#define MSR_IA32_EXT_XAPICID 0x00000802 /* x2APIC ID */
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#define MSR_IA32_EXT_APIC_VERSION 0x00000803 /* x2APIC version */
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#define MSR_IA32_EXT_APIC_TPR 0x00000808
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/* x2APIC task priority */
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#define MSR_IA32_EXT_APIC_PPR 0x0000080A
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/* x2APIC processor priority */
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#define MSR_IA32_EXT_APIC_EOI 0x0000080B /* x2APIC EOI */
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#define MSR_IA32_EXT_APIC_LDR 0x0000080D
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/* x2APIC logical destination */
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#define MSR_IA32_EXT_APIC_SIVR 0x0000080F
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/* x2APIC spurious interrupt vector */
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#define MSR_IA32_EXT_APIC_ISR0 0x00000810
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/* x2APIC in-service register 0 */
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#define MSR_IA32_EXT_APIC_ISR1 0x00000811
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/* x2APIC in-service register 1 */
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#define MSR_IA32_EXT_APIC_ISR2 0x00000812
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/* x2APIC in-service register 2 */
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#define MSR_IA32_EXT_APIC_ISR3 0x00000813
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/* x2APIC in-service register 3 */
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#define MSR_IA32_EXT_APIC_ISR4 0x00000814
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/* x2APIC in-service register 4 */
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#define MSR_IA32_EXT_APIC_ISR5 0x00000815
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/* x2APIC in-service register 5 */
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|
#define MSR_IA32_EXT_APIC_ISR6 0x00000816
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|
/* x2APIC in-service register 6 */
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|
#define MSR_IA32_EXT_APIC_ISR7 0x00000817
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|
/* x2APIC in-service register 7 */
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#define MSR_IA32_EXT_APIC_TMR0 0x00000818
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/* x2APIC trigger mode register 0 */
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#define MSR_IA32_EXT_APIC_TMR1 0x00000819
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/* x2APIC trigger mode register 1 */
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#define MSR_IA32_EXT_APIC_TMR2 0x0000081A
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|
/* x2APIC trigger mode register 2 */
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|
#define MSR_IA32_EXT_APIC_TMR3 0x0000081B
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|
/* x2APIC trigger mode register 3 */
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|
#define MSR_IA32_EXT_APIC_TMR4 0x0000081C
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|
/* x2APIC trigger mode register 4 */
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|
#define MSR_IA32_EXT_APIC_TMR5 0x0000081D
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|
/* x2APIC trigger mode register 5 */
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|
#define MSR_IA32_EXT_APIC_TMR6 0x0000081E
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|
/* x2APIC trigger mode register 6 */
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|
#define MSR_IA32_EXT_APIC_TMR7 0x0000081F
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|
/* x2APIC trigger mode register 7 */
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|
#define MSR_IA32_EXT_APIC_IRR0 0x00000820
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|
/* x2APIC interrupt request register 0 */
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|
#define MSR_IA32_EXT_APIC_IRR1 0x00000821
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|
/* x2APIC interrupt request register 1 */
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|
#define MSR_IA32_EXT_APIC_IRR2 0x00000822
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|
/* x2APIC interrupt request register 2 */
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|
#define MSR_IA32_EXT_APIC_IRR3 0x00000823
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|
/* x2APIC interrupt request register 3 */
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|
#define MSR_IA32_EXT_APIC_IRR4 0x00000824
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|
/* x2APIC interrupt request register 4 */
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|
#define MSR_IA32_EXT_APIC_IRR5 0x00000825
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|
/* x2APIC interrupt request register 5 */
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|
#define MSR_IA32_EXT_APIC_IRR6 0x00000826
|
|
/* x2APIC interrupt request register 6 */
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|
#define MSR_IA32_EXT_APIC_IRR7 0x00000827
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|
/* x2APIC interrupt request register 7 */
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|
#define MSR_IA32_EXT_APIC_ESR 0x00000828
|
|
/* x2APIC error status */
|
|
#define MSR_IA32_EXT_APIC_LVT_CMCI 0x0000082F
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|
/* x2APIC LVT corrected machine check interrupt register */
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|
#define MSR_IA32_EXT_APIC_ICR 0x00000830
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|
/* x2APIC interrupt command register */
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|
#define MSR_IA32_EXT_APIC_LVT_TIMER 0x00000832
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|
/* x2APIC LVT timer interrupt register */
|
|
#define MSR_IA32_EXT_APIC_LVT_THERMAL 0x00000833
|
|
/* x2APIC LVT thermal sensor interrupt register */
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|
#define MSR_IA32_EXT_APIC_LVT_PMI 0x00000834
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|
/* x2APIC LVT performance monitor interrupt register */
|
|
#define MSR_IA32_EXT_APIC_LVT_LINT0 0x00000835
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|
/* x2APIC LVT LINT0 register */
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|
#define MSR_IA32_EXT_APIC_LVT_LINT1 0x00000836
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|
/* x2APIC LVT LINT1 register */
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|
#define MSR_IA32_EXT_APIC_LVT_ERROR 0x00000837
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|
/* x2APIC LVT error register */
|
|
#define MSR_IA32_EXT_APIC_INIT_COUNT 0x00000838
|
|
/* x2APIC initial count register */
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|
#define MSR_IA32_EXT_APIC_CUR_COUNT 0x00000839
|
|
/* x2APIC current count register */
|
|
#define MSR_IA32_EXT_APIC_DIV_CONF 0x0000083E
|
|
/* x2APIC divide configuration register */
|
|
#define MSR_IA32_EXT_APIC_SELF_IPI 0x0000083F
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|
/* x2APIC self IPI register */
|
|
#define MSR_IA32_EFER 0xC0000080
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|
/* Extended feature enables */
|
|
#define MSR_IA32_STAR 0xC0000081
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|
/* System call target address */
|
|
#define MSR_IA32_LSTAR 0xC0000082
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|
/* IA-32e mode system call target address */
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|
#define MSR_IA32_FMASK 0xC0000084
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|
/* System call flag mask */
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|
#define MSR_IA32_FS_BASE 0xC0000100
|
|
/* Map of BASE address of FS */
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|
#define MSR_IA32_GS_BASE 0xC0000101
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|
/* Map of BASE address of GS */
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|
#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
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|
/* Swap target of BASE address of GS */
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|
#define MSR_IA32_TSC_AUX 0xC0000103 /* Auxiliary TSC */
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|
|
|
/* ATOM specific MSRs */
|
|
#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
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|
/* Processor hard power-on configuration */
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|
#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
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|
/* Last branch record 0 from IP */
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|
#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
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|
/* Last branch record 1 from IP */
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|
#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
|
|
/* Last branch record 2 from IP */
|
|
#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
|
|
/* Last branch record 3 from IP */
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|
#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
|
|
/* Last branch record 4 from IP */
|
|
#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
|
|
/* Last branch record 5 from IP */
|
|
#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
|
|
/* Last branch record 6 from IP */
|
|
#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
|
|
/* Last branch record 7 from IP */
|
|
#define MSR_ATOM_LASTBRANCH_0_TO_LIP 0x00000060
|
|
/* Last branch record 0 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_1_TO_LIP 0x00000061
|
|
/* Last branch record 1 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_2_TO_LIP 0x00000062
|
|
/* Last branch record 2 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_3_TO_LIP 0x00000063
|
|
/* Last branch record 3 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_4_TO_LIP 0x00000064
|
|
/* Last branch record 4 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_5_TO_LIP 0x00000065
|
|
/* Last branch record 5 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_6_TO_LIP 0x00000066
|
|
/* Last branch record 6 to IP */
|
|
#define MSR_ATOM_LASTBRANCH_7_TO_LIP 0x00000067
|
|
/* Last branch record 7 to IP */
|
|
#define MSR_ATOM_FSB_FREQ 0x000000CD /* Scalable bus speed */
|
|
#define MSR_PLATFORM_INFO 0x000000CE
|
|
/* Maximum resolved bus ratio */
|
|
#define MSR_ATOM_BBL_CR_CTL3 0x0000011E /* L2 hardware enabled */
|
|
#define MSR_ATOM_THERM2_CTL 0x0000019D
|
|
/* Mode of automatic thermal monitor */
|
|
#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
|
|
/* Last branch record stack TOS */
|
|
#define MSR_ATOM_LER_FROM_LIP 0x000001DD
|
|
/* Last exception record from linear IP */
|
|
#define MSR_ATOM_LER_TO_LIP 0x000001DE
|
|
/* Last exception record to linear IP */
|
|
|
|
/* LINCROFT specific MSRs */
|
|
#define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0 /* Configure CAR */
|
|
|
|
/* EFER bits */
|
|
#define MSR_IA32_EFER_SCE_BIT (1<<0)
|
|
#define MSR_IA32_EFER_LME_BIT (1<<8) /* IA32e mode enable */
|
|
#define MSR_IA32_EFER_LMA_BIT (1<<10) /* IA32e mode active */
|
|
#define MSR_IA32_EFER_NXE_BIT (1<<11)
|
|
|
|
/* FEATURE CONTROL bits */
|
|
#define MSR_IA32_FEATURE_CONTROL_LOCK (1<<0)
|
|
#define MSR_IA32_FEATURE_CONTROL_VMX_SMX (1<<1)
|
|
#define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1<<2)
|
|
|
|
/* PAT memory type definitions */
|
|
#define PAT_MEM_TYPE_UC 0x00 /* uncached */
|
|
#define PAT_MEM_TYPE_WC 0x01 /* write combining */
|
|
#define PAT_MEM_TYPE_WT 0x04 /* write through */
|
|
#define PAT_MEM_TYPE_WP 0x05 /* write protected */
|
|
#define PAT_MEM_TYPE_WB 0x06 /* writeback */
|
|
#define PAT_MEM_TYPE_UCM 0x07 /* uncached minus */
|
|
|
|
/* MTRR memory type definitions */
|
|
#define MTRR_MEM_TYPE_UC 0x00 /* uncached */
|
|
#define MTRR_MEM_TYPE_WC 0x01 /* write combining */
|
|
#define MTRR_MEM_TYPE_WT 0x04 /* write through */
|
|
#define MTRR_MEM_TYPE_WP 0x05 /* write protected */
|
|
#define MTRR_MEM_TYPE_WB 0x06 /* writeback */
|
|
|
|
/* misc. MTRR flag definitions */
|
|
#define MTRR_ENABLE 0x800 /* MTRR enable */
|
|
#define MTRR_FIX_ENABLE 0x400 /* fixed range MTRR enable */
|
|
#define MTRR_VALID 0x800 /* MTRR setting is valid */
|
|
|
|
/* SPEC & PRED bit */
|
|
#define SPEC_ENABLE_IBRS (1<<0)
|
|
#define SPEC_ENABLE_STIBP (1<<1)
|
|
#define PRED_SET_IBPB (1<<0)
|
|
|
|
#endif /* MSR_H */
|