Commit Graph

1460 Commits

Author SHA1 Message Date
Mingqiang Chi de487fff2b hv:fix return value violations for vpic/vioapic
-- Change these APIs to void type, add pre-conditions,
   and move parameter-check to upper-layer functions.
   handle_vpic_irqline
   vpic_set_irqstate
   vpic_assert_irq
   vpic_deassert_irq
   vpic_pulse_irq
   vpic_get_irq_trigger
   handle_vioapic_irqline
   vioapic_assert_irq
   vioapic_deassert_irq
   vioapic_pulse_irq
-- Remove dead code
   vpic_set_irq_trigger

v1-->v2:
   add cleanup vpic
   change some APIs to void type, add pre-conditions,
   and move the parameter-check to upper-layer functions.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-16 09:01:08 +08:00
ailin,yang cad8492a12 enable weston to fix: #663
add user and enable weston service to fix issue: #663
2018-08-15 05:08:29 -07:00
Jason Chen CJ f2a3e1fb76 quick fix: fix build failure for release version
conflicting types for ‘vcpu_dumpreg’

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-15 13:47:01 +08:00
Victor Sun bb5377b354 HV: change wake vector info to accommodate ww32 sbl
The wake vector address in SBL ACPI table was changed since ww30,
so change platform acpi info accordingly to support system S3.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 12:20:28 +08:00
Jason Chen CJ f8f49d410f dump vcpu registers on correct vcpu
after updated cpu context get/set method, the vcpu_dumreg cmd is not
correct anymore as the registers may read from VMCS but meantime hv
shell may not be running on target vcpu.

this patch take use of smp_call_function for vcpu dumpreg and make the
dump always come from correct vcpu.

v2:
- use str pointer to get vcpu_dumpreg context instead of print out directly
  in notify handler.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 12:05:18 +08:00
Jason Chen CJ 4b03c97a5e add smp_call_function support
take use of VCPU_NOTIFY vector, add smp_call_function support.
added a per_cpu field smp_call_info, and make each smp_call_function
is not re-entered, and the caller CPU is returned when all the target
CPUs complete the call.

v4:
- remove global lock
- take use of wait_sync_change function to do the sequence sync

v3:
- remove per_cpu lock in smp_call_info
- use a global lock to ensure smp_call_function sequence
- use pcpu_sync_sleep to wait IPI complete

v2:
- after new smp function come, if old one exist, changed from overwirte
  with the new one to ignore the new one.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-15 12:05:18 +08:00
Jason Chen CJ 8ef072165f idle: enable IRQ in default idle
we should let cpu handle IRQ during idle

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-15 12:05:18 +08:00
Jason Chen CJ e19d36fa6c change pcpu_sync_sleep to wait_sync_change
pcpu_sync_sleep monitor "uint64_t sync" change to "1UL << mask_bit",
which is not very clear to take use of it.
change it to wait_sync_change, means monitor "uint64_t sync" change to
"wake_sync", make the function clear to use.
And expose it for the usage of the following patches.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-15 12:05:18 +08:00
Jason Chen CJ 49d3446861 lapic: add send_dest_ipi function
send_dest_ipi is trying to send ipi to dest with a group.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-15 12:05:18 +08:00
Junjie Mao 6e96243b01 HV: io: drop REQ_STATE_FAILED
Now the DM has adopted the new VHM request state transitions and
REQ_STATE_FAILED is obsolete since neither VHM nor kernel mediators will set the
state to FAILED.

This patch drops the definition to REQ_STATE_FAILED in the hypervisor, makes
''processed'' unsigned to make the compiler happy about typing and simplifies
error handling in the following ways.

* (dm_)emulate_(pio|mmio)_post no longer returns an error code, by introducing a
  constraint that these functions must be called after an I/O request
  completes (which is the case in the current design) and assuming
  handlers/VHM/DM will always give a value for reads (typically all 1's if the
  requested address is invalid).

* emulate_io() now returns a positive value IOREQ_PENDING to indicate that the
  request is sent to VHM. This mitigates a potential race between
  dm_emulate_pio() and pio_instr_vmexit_handler() which can cause
  emulate_pio_post() being called twice for the same request.

* Remove the ''processed'' member in io_request. Previously this mirrors the
  state of the VHM request which terminates at either COMPLETE or FAILED. After
  the FAILED state is removed, the terminal state will always be constantly
  COMPLETE. Thus the mirrored ''processed'' member is no longer useful.

Note that emulate_instruction() will always succeed after a reshuffle, and this
patch takes that assumption in advance. This does not hurt as that returned
value is not currently handled.

This patch makes it explicit that I/O emulation is not expected to fail. One
issue remains, though, which occurs when a non-aligned cross-boundary access
happens. Currently the hypervisor, VHM and DM adopts different policy:

* Hypervisor: inject #GP if it detects that the access crossed boundary

* VHM: deliver to DM if the access does not complete falls in the range of a
  client

* DM: a handler covering part of the to-be-accessed region is picked and
  assertion failure can be triggered.

A high-level design covering all these components (in addition to instruction
emulation) is needed for this. Thus this patch does not yet cover the issue.

Tracked-On: #875
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 12:04:12 +08:00
Junjun Shan ca83c09b9f hv: treewide: fix multiple MISRAC violations
MISARC has requirements about  Marco redefinition, usage of ++ or -- and
assignment operator in boolean expression. This patch is used to solve
these violations.

The modifications are summarized as following:
1.The HC_VM_SET_MEMORY_REGION, HC_VM_GPA2HPA, HC_VM_SET_MEMORY_REGIONS are
redefined twice in acrn_hv_des.h, so delete them to solve the macro
redefinition violations.

2.The macro BUS_LOCK are redefined in bits.h and atomic.h, then delete
the declaration in both two files, add a new declaration in cpu.h and
include the header file.

3.modify the code to solve the improper usage of -- operators in string.c.

4.modify the while loop to for loop to avoid assignment operator in
boolean expression in vlapic.c.

v1 -> v2:
 *Modify the format of commit logs and signed-off name.

 *Modify the code format from 'd = d-1;' to 'd--;' to be better.

Signed-off-by: Junjun Shan <junjun.shan@intel.com>
2018-08-15 11:21:09 +08:00
Xiaoguang Wu 0292e14ff9 DM USB: xHCI: enable xHCI SOS S3 support
This patch enable the support for SOS S3 from the perspective
of USB xHCI.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu 0b405ee780 DM USB: xHCI: change flow of creation of virtual USB device
The xHCI emulation greatly depends on the user space library libusb
which is based on the usbfs module in Linux kernel. The libusb will
bind usbfs to physical USB device which makes hardware control over
libusb in user space possible.

The pci_xhci_dev_create is called in pci_xhci_native_usb_dev_conn_cb
which is a callback function triggered by physical USB device plugging.
This function will bind the physical USB device to usbfs in SOS, which
we depend to create the communication between UOS xHCI driver with
physical USB device.

This design will fail if the reconnection happened in the SOS, which
will bind class driver to the physical USB device instead of usbfs,
hence the libusb device handle in DM is invalid.

Currently, the native S3 will disable the vbus for all xHCI ports and
re-drive during S3 resume. This behavior cause native USB driver unbind
the usbfs and bind to related class driver, then made the DM lost
control and failed to continue emulation.

To fix this issue, place the pci_xhci_dev_create in the function
pci_xhci_cmd_enable_slot. According to the xHCI spec 4.5.3 Figure 10,
the UOS always send Enable Slot command when a device is attached or
recovered from errors (by Disable Slot command). So every time the SOS
can't resuming normally or some unexpected disconnection happens, this
desigen will always survive by Disable Slot and Enable Slot command
series from UOS xHCI driver.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu b359dc361a DM USB: xHCI: code cleanup: change variable name
Replace 'native_assign_ports' with 'port_map_tbl' to be more accurate
for the role of this variable plays.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu 27eeea4cd3 DM USB: xHCI: refine port assignment logic
The variable native_assign_ports in struct pci_xhci_vdev is used
to record wether certain root hub port in SOS is assigned to UOS.
The logic uses zero to express 'not assigned' and nonzero to express
'assigned'. In this patch, use macro to replace number to express
better.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu 5cc389aa29 DM USB: xHCI: limit bus and port numbers of xHCI
Currently the maximum number of bus and port for xHCI are
both set to 255, it is theoretically possible but in fact
not neccessary. This patch changes those two values to be
more proper: 4 buses and 20 ports.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu 2abec44e15 DM USB: introduce struct usb_native_devinfo
Current design cannot get physical USB device information without
the creation of pci_xhci_dev_emu. This brings some difficulties in
certain situations, hence struct usb_native_devinfo is introduced
to describe neccessary information to solve this trouble.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu 363b4da4df DM USB: xHCI: refine xHCI PORTSC Register related functions
PORTSC (Port Status and Control Register) register play a very
important role in USB sub-system. This patch is used to refine
related manipulation functions.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Xiaoguang Wu b746377f45 DM USB: xHCI: fix an xHCI issue to enable UOS s3 feature
Current DM design use two variables to do the indexing of xHCI
Event Ring: er_enq_idx and er_events_cnt. They are members of
the struct pci_xhci_rtsregs.

In UOS, during the process of xHCI resuming, the xHCI driver
will restore the ERSTBA (Event Ring Segment Table Base Address)
register to be the value before suspending. And at this point,
the old DM implementation will set both er_enq_idx and
er_events_cnt to be zero, so the DM will access the Event Ring
from the start position in the buffer. But at the same time the
UOS xHCI driver still wants to access the old position in the
Event Ring before suspending, which will result of unexpected
errors.

Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-08-15 11:18:33 +08:00
Kaige Fu b5a233da9f HV: Enclose debug specific code with #ifdef HV_DEBUG
Thare some debug specific code which don't run on release version, such as vmexit_time,
vmexit_cnt, sbuf related codes, etc...

This patch encloses the codes with #ifdef HV_DEBUG.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 11:17:29 +08:00
yuhong.tao@intel.com b0861621d9 dm: monotor: bugfix: update wakeup reason before call recume() callback
In handle_resume(), wakeup_reason is updated before call
ops->ops->resume(). Because ops->ops->resume() needs to know the
latest wakeup reason.

Acked-by: Yan Like <like.yan@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-08-15 11:16:54 +08:00
yuhong.tao@intel.com a86a25f369 tools: acrnd: Fixed get_sos_wakeup_reason()
get_sos_wakeup_reason() runs into error branch without any error, so
no wakeup reason will be returend.

Acked-by: Yan Like <like.yan@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-08-15 11:16:54 +08:00
yuhong.tao@intel.com 2d802d0afe tools: vm_resume() requires wakeup reason
DM need to know wakeup reason when resume the VM, so
vm_resume(char *name) is updated to vm_resume(char *name, unsigned reason),
in acrn_vm_ops.c

Acked-by: Yan Like <like.yan@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-08-15 11:16:54 +08:00
Jason Chen CJ 64a9b2b423 Revert "[REVERT-ME]: disable turbo mode"
This reverts commit b3690987bd.
2018-08-15 11:05:49 +08:00
Kaige Fu 18d44cc928 tools: acrnalyze: Make the result easier to read
Originally, we don't format the output of analyser well. It is hard to read the
result.

This patch make every entry of the result align with the corresponding title to
make it easier for users to read.

Without patch:
Event                    NR_Exit         NR_Exit/Sec     Time Consumed(cycles)       Time Percentage
VMEXIT_INTERRUPT_WINDOW         78090   130.15  40      0.01
VMEXIT_CR_ACCESS        0       0.00    0       0.00
VMEXIT_APICV_ACCESS     0       0.00    0       0.00
VMEXIT_EXCEPTION_OR_NMI         0       0.00    0       0.00
VMEXIT_RDTSC    0       0.00    0       0.00

...

Vector          Count   NR_Exit/Sec
0x000000f0       82337  137.23
0x000000ef       247713         412.85

With patch:
Event                           NR_Exit         NR_Exit/Sec     Time Consumed(cycles)           Time percentage
VMEXIT_APICV_WRITE              13352           22.25           14331304                        0.00
VMEXIT_WRMSR                    309085          515.14          241166212                       0.02
VMEXIT_INTERRUPT_WINDOW         78090           130.15          76841734                        0.01

...

Vector          Count           NR_Exit/Sec
0x000000f0      82337           137.23
0x000000ef      247713          412.85

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Yan, Like <like.yan@intel.com>
2018-08-15 10:59:31 +08:00
Yan, Like 08dd698d99 hv: pirq: rename common irq APIs
This commit cleans up the irq APIs which are a bit confusing.
 - pri_register_handler(), normal_register_handler() and
   common_register_handler() into request_irq(), and removed
   the unnecessary struct irq_request_info;
 - rename the unregister_common_handler() to free_irq();

After the revision, the common irq APIs becomes:
 - int32_t request_irq(uint32_t irq,
                    irq_action_t action_fn,
                    void *action_data,
                    const char *name)

 - void free_irq(uint32_t irq)

Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-15 10:40:43 +08:00
Yan, Like 8fda0d8c5f hv: pirq: add static irq:vector mappings
Since vector is x86 specific concept, we'd like to hide it from common irq APIs.
This commit
 - adds static irq:vector mappings for special interrupt such as timer
and cpu notification;
 - reserves the irq and vector at initialization;
 - removed the vector argument in pri_register_handler(), get reserved vector
   from irq_desc in common_register_handler().

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-15 10:40:43 +08:00
Yan, Like f6e45c9b13 hv: pirq: remove unnecessary dev_handler_node struct
Since we don't support shared irq, dev_handler_node which works as action node,
is not needed anymore.

This commit removes the dev_handler_node struct and does some relevant changes,
including:
 - moves necessary fields to struct irq_desc: action, priv_data, name; and
   removes unused handler_data;
 - changes return type of pri_/normal_register_handler() from dev_handler_node*
   to int32_t, which is irq num (>= 0) on success, and errno (> 0) on failure.
 - changes unregister_irq_handler() to take argument unint32_t instead of
   dev_handler_node*;
 - changes are made to the places where these APIs are called.

Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Eddie Dong  <eddie.dong@intel.com>
2018-08-14 16:48:45 +08:00
Yan, Like d773df9135 hv: pirq: remove support of physical irq sharing
Because multiple physical devices sharing a single physical pin would be
assigned to a same VM, so UOS could handle the irq sharing. So that we could
remove the physical irq sharing support in HV.

This commit removes the irq sharing support, changes including:
 - removed the dev_list field in irq_desc, and clean up codes for the list
   operation;
 - replace IRQ_ASSIGNED_SHARED and IRQ_ASSIGNED_NOSHARE with IRQ_ASSIGNED;
 - remove argument indicating irq is shared;
 - revise irq request flow for pt devices to remove dependency on irq sharing:
   register irq on adding remapping entery and unregister irq on removal an
   entry, and do not register/unregister at remapping an entry.

Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-14 16:48:45 +08:00
Shiqing Gao 6744a179fc hv: treewide: fix 'Shifting value too far'
MISRA-C requires that shift operation cannot exceed the word length.

What this patch does:
- Add the pre condition for 'init_lapic' regarding to 'pcpu_id'
  Currently, max 8 physical cpus are supported.
  Re-design will be required if we would like to support more physical
   cpus.
  So, add the pre condition here to avoid the unintentional shift
   operation mistakes.

- Replace the id type with uint8_t in 'vlapic_build_id'
  - For VM0, it uses 'lapic_id' as its id, which is uint8_t.
  - For non VM0, it uses 'vcpu_id' as its id, which is uint16_t.
    Cast this id to uint8_t to make sure there is no loss of data after
     left shifting 24U.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:05:44 +08:00
Binbin Wu a9151ff3fa hv: add compile time assert for static checks
Add two files to do compile time assert.
One is arch specific, and put in hypervisor/arch/x86/.
The other one is common, and put in hypervisor/common/.

If the statement is not true, there will be error during compile time.
The file will not increase the size of HV binary.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:05:06 +08:00
Binbin Wu 69522dc861 hv: move boot_ctx offset definitions
Move the definitions of offset of fields in boot_ctx to the same header
file that the struct boot_ctx is in, to reduce the possibility that some
modification would make the offset inconsistant with the fields within
the structure.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:05:06 +08:00
Zhao Yakui 197706ff16 HV: Use the CPUID(0x16) to obtain tsc_hz when zero tsc_hz is returned by 0x15 cpuid
Sometimes the CPUID(0x15) still returns the zero tsc frequency. In such case
the base frequency of cpuid(0x16) is used as tsc frequency.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:04:21 +08:00
Zhao Yakui 7d83abb4a5 HV: Add the emulation of CPUID with 0x16 leaf
The CPUID with 0x16 leaf can report the CPU hz and it is faster. And this
mechanism is widely used in Linux kernel.(native_calibrate_cpu).
As this is not supported on APL, currently sos adds the cpu_khz callback
in pv_cpu_ops to read the cpu frequency. This is quite hack.
(In fact HV leverages the cpuid with 0x40000010 leaf).
If it is emulated, the sos and guest os can use the cpuid to obtain the
corresponding cpu_khz. Then the cpu_khz in pv_cpu_ops can be removed.

V2: Simple the logic of adding unsupported cpuid level entry after the
CPUID 0x16 is emulated. Initialize the vcpuid_entry explicitly with zero
for the unsupported cpuid.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:04:21 +08:00
Zhao Yakui e0eeb8a558 HV: Limit the CPUID with >= 0x15 leaf
In order to add the emulation of CPUID 0x16, it is expected that it is
handled when the CPUID 0x15 is supported. Otherwise we will have to emulate
other CPUID leaf, which makes it complex.
At the same time as Acrn HV has the requirements on the CPUs, it is restricted
that the CPUID should support the leaf >=0x15.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:04:21 +08:00
Kaige Fu d5d3d2d2a8 tools: acrnlog: Add [-t interval] [-h] to usage
This patch add "[-t interval] [-h]" which support by acrnlog now to usage.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Like Yan <like.yan@intel.com>
2018-08-14 10:01:18 +08:00
Kaige Fu a9a2f91353 tools: acrntrace: Remove unused paramters "-r" related things
Option "-r" has been removed by commit 3d6ff0e (tools: acrntrace: save trace
data file under current dir by default). But leaves something unused in optstring
and README.rst.

This patch remove thest related things.

BTW, this patch refine the usage output to print [-t max_time].

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Reviewed-by: Like Yan <like.yan@intel.com>
2018-08-14 10:01:18 +08:00
Victor Sun 76e43ac7ce HV: handle trusty on vm reset
- clear run context when reset vcpu;

- destroy trusty without erase trusty memory when reset vm;

changelog:
	v1 -> v2: fix misra violation on calling memset();

Signed-off-by: Sun Victor <victor.sun@intel.com>
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Chi Mingqiang <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 09:55:58 +08:00
Yonghua Huang c55b696a92 HV: remove 'warm_reboot()'function and other minor cleanup
- 'reboot.c' defines 'warm_reboot()' only, and this
    function is deprecated.
  - remove the eXecution attribute of 'mttr.h'

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 09:54:48 +08:00
Yonghua Huang 77011ce60e HV: Merge hypervisor debug header files
-- merge 'assert.h' & 'printf.h' into 'logmsg.h'
  -- merge 'shell.h' into 'console.h'

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 09:54:48 +08:00
Yonghua Huang a6bc36f8ed HV: refine shell.c & shell_priv.h
- move local functions declarations to shell.c
- remove 'name' field in 'struct shell' as i/o
  session s/w layer is deprecated.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 09:54:48 +08:00
Yonghua Huang 28c8923084 HV: rename 'shell_internal.h' to 'shell_priv.h'
- to align the coding style in hypervisor

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 09:54:48 +08:00
Yang, Yu-chu 2fbf70780e HV: Logical conjunction needs brackets
The bracket is required when the level of precedence of
the operators is less than 13. Add the bracket to logical
conjunctions. The commit applys the rule to the files under

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-14 09:53:32 +08:00
Yang, Yu-chu 6f1c5fa007 HV: Logical conjunction needs brackets under /arch/x86/guest
The bracket is required when the level of precedence of
the operators is less than 13. Add the bracket to logical
conjunctions. The commit applys the rule to the files under
hypervisor/arch/x86/guest/*

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-14 09:53:32 +08:00
Bandi,Kushal 7a739ccef0 DM: Add dm for IPU mediation
This device model is to configure the virtual IPU PCI device.
In order to execute this DM the lauch script needs to add
virtio-ipu as parameter to acrn-dm
For e.g. -s 21,virtio-ipu

Signed-off-by: Bandi,Kushal <kushal.bandi@intel.com>
2018-08-13 16:18:49 +08:00
Binbin Wu a568c9e3f7 dm: bios: update vsbl to v0.8.1
Support trusty S3 resume.
New watchdog reset report value.
Increase the limitation of bzImage size.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
2018-08-13 14:28:58 +08:00
ailin,yang 5a559ce6f5 fixed cpu info incorrect and remove 2M hugepages
with original script, user can not get 3 CPU cores info with cat/proc/cpuinfo in UOS.
it just show 1 only.  with this patch,  default,  user can see 1 cpu info in SOS and 3 cores info in UOS.
and remove 2M hugepages settings because it is not using any more.
# make sure there is enough 2M hugepages in the pool
echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages
also, this patch is setting default UOS memory to 2G
2018-08-13 14:27:19 +08:00
ailin,yang f11b2635c5 remove 2M hugepages
remove 2M hugepages setting here because it will not use any more. 
# make sure there is enough 2M hugepages in the pool
echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages
2018-08-13 14:24:10 +08:00
Minggui Cao 462284fa7d HV: add pcpu id check before send IPI
to avoid send IPI to self, also improve the related code:
1. get_cpu_id is uint16_t now
2. MISRA-C requirement. like add {}

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-13 14:07:30 +08:00
Sainath Grandhi c25a62e5b0 hv: Create E820 entries for OS in partitioning mode ACRN
1) This patch creates static E820 entries for VMs launced by ACRN in
partition mode.
2) Moves vm_description entries from bsp/sbl/ to partition/
3) Removes unused API get_vm_desc_base

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-13 13:58:32 +08:00