Commit Graph

5752 Commits

Author SHA1 Message Date
Shiqing Gao 76017ec67f doc: update coding guidelines
- add a rule for function parameter limit

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2020-10-30 08:36:21 -07:00
David B. Kinder 62d0088565 doc: doc spelling and grammer fixing
Continuing with additional spelling and grammar fixes missed during
retular reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-10-30 08:32:53 -07:00
Shixiong Zhang 22c5dd2c58 acrn-config: fix the wrong vuart name in launch script
when fix the issue of _PM_SystemS5 with life_mngr fail,
the vuart1(tty) item was devided into two parts, the last
part "/dev/tty*" which need to get will be added to the
end, so it should be handled singly, but it will be added
to other item too, such as vuart1(pty).

Tracked-On:#5366

Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
2020-10-30 21:09:27 +08:00
Mingqiang Chi 0eb50e5668 cleanup vpci structure when shutdown_vm
cleanup vpci structure when shutdown_vm to avoid use uninitialized data
after reboot.

Tracked-On: #4958
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-30 20:48:37 +08:00
Tao Yuhong 996e8f680c HV: pci-vuart support create vdev hcall
Add cteate method for vmcs9900 vdev in hypercalls.

The destroy method of ivshmem is also suitable for other emulated vdev,
move it into hcall_destroy_vdev() for all emulated vdevs

Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-30 20:41:34 +08:00
Tao Yuhong a371815462 dm: pci uart support create vuart-pci at HV land
If acrn-dm create pci vuart with
'-s,<slot>,uart,vuart_idx:<value>', then acrn-dm will not
create pci uart at DM land, but create an vuart-pci virtual device
at HV land.
When create a HV land vuart-pci vdev, user must specify its vuart id.
Which is defined in vm_config, is the acrn_vm_pci_dev_config.vuart_idx

Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-30 20:41:34 +08:00
Tao Yuhong 691abe90ff HV: vuart: send msi for pci vuart type
if vuart type is pci-vuart, then use MSI interrupt

split vuart_toggle_intr() control flow into vuart_trigger_level_intr() &
trigger_vmcs9900_msix(), because MSI is edge triggered, no deassertion
operation. Only trigger MSI for pci-vuart when assert interrupt.

Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-10-30 20:41:34 +08:00
Tao Yuhong 55b7fae67a HV: pci-vuart: pci based vuart emulation
Add emulation for pci based vuart device mcs9900 at hv land.
add struct pci_vdev_ops vuart_pci_ops, the vdev callbalks for vuart.

How to use
In misc/vm_configs/scenarios/<SCENARIO>/<BOARD>/pci_dev.c, add pci
vuart config to vm_pci_devs[] array. For example:

struct acrn_vm_pci_dev_config vm0_pci_devs[] = {
       /* console vuart setting*/
       {
               .emu_type = PCI_DEV_TYPE_HVEMUL,
               .vbdf.bits = {.b = 0x00U, .d = 0x04U, .f = 0x00U},
               .vdev_ops = &vmcs_ops,
               .vbar_base[0] = 0x80001000,	/* mmio bar */
               .vbar_base[1] = 0x80002000,	/* msix bar */
               .vuart_idx = 0,
       },
       /* communication vuart setting */
       {
               .emu_type = PCI_DEV_TYPE_HVEMUL,
               .vbdf.bits = {.b = 0x00U, .d = 0x05U, .f = 0x00U},
               .vdev_ops = &vmcs_ops,
               .vbar_base[0] = 0x80003000,
               .vbar_base[1] = 0x80004000,
               .vuart_idx = 1,
               .t_vuart.vm_id = 1U,
               .t_vuart.vuart_id = 1U,
       },
}

Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-10-30 20:41:34 +08:00
Tao Yuhong 4120bd391a HV: decouple legacy vuart interface from acrn_vuart layer
support pci-vuart type, and refine:
1.Rename init_vuart() to init_legacy_vuarts(), only init PIO type.
2.Rename deinit_vuart() to deinit_legacy_vuarts(), only deinit PIO type.
3.Move io handler code out of setup_vuart(), into init_legacy_vuarts()
4.add init_pci_vuart(), deinit_pci_vuart, for one pci vuart vdev.

and some change from requirement:
1.Increase MAX_VUART_NUM_PER_VM to 8.

Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-30 20:41:34 +08:00
Tao Yuhong 6ed7b8767c HV: vuart: refine vuart read/write
The vuart_read()/vuart_write() are coupled with PIO vuart type. Move
the non-type related code into vuart_read_reg()/vuart_write_reg(), so
that we can re-use them to handle MMIO request of pci-vuart type.

Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-30 20:41:34 +08:00
Yang,Yu-chu 8e545734d4 acrn-config: fix the bug of resolved nested mmio address
Multiple devices could be nested under the same range. Skip remove if
the device is removed already

Tracked-On: #5437
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2020-10-30 20:40:16 +08:00
Liang Yi 5646b218ff acrn-config: minor change scenario xml for cfl-k700-i7
Changes:
	1. assign 3 CPUs for WaaG on hybrid_rt scenario;
	2. Passthrough NVME@9:0.0 for VM0 on hybrid_rt scenario;
	3. Change rootfs from partition2 to partition3;

Tracked-On: #5390

Signed-off-by: Liang Yi <yi.liang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
2020-10-30 20:38:43 +08:00
Yang,Yu-chu 7f80314406 acrn-config: find unused vbar base from start to end
- find unused vbar base from start of the memory address

Tracked-On: #5426
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
2020-10-30 20:24:28 +08:00
Yang,Yu-chu 6fa5e10e93 acrn-config: fix the shmem vbar2 with prefechtable bit
BAR2 is sharing memory bar:
- set bit[3] Prefetchable
- bit [2:1] to 10b

Tracked-On: #5426
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
2020-10-30 20:24:28 +08:00
Yang,Yu-chu c2f1d65ace acrn-config: add vbar[1] to SOS and pre-launched VM
Add vbar base region 1 for SOS and pre-launched VM ivshmem

Tracked-On: #5426
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
2020-10-30 20:24:28 +08:00
Yang,Yu-chu 2290396ef5 acrn-config: generate SOS ivshmem device information
Support enable ivshmem for SOS. Insert the ivshmem device information if
it is enabled.
1. get ivshmem vbar based:
  - vbar[0] is size 0x100
  - vbar[2] is specified MB size
2. get vbdf for ivshmem device

Tracked-On: #5426
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
2020-10-30 20:24:28 +08:00
Yang, Yu-chu 0f16746c1e acrn-config: add sos pci_dev_num and pci_devs to vm_configurations.c
Add following to default output scenarios vm_configurations.c:
 - pci_dev_num
 - pci_devs = sos_pci_devs

Both was defineded in CONFIG_SOS_VM.

Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2020-10-30 20:24:28 +08:00
Yang, Yu-chu 57ed333027 acrn-config: fix logical of vm total pci devices count
Skip vhostbridge if there is no pci passtrhough device

Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2020-10-30 20:24:28 +08:00
Yang, Yu-chu 8c78590da7 acrn-config: refactor pci_dev_c.py and insert vuart device information
- Refactor pci_dev_c.py to insert devices information per VMs
- Add function to get unused vbdf form bus:dev.func 00:00.0 to 00:1F.7

Add pci devices variables to vm_configurations.c
- To pass the pci vuart information form tool, add pci_dev_num and
pci_devs initialization by tool
- Change CONFIG_SOS_VM in hypervisor/include/arch/x86/vm_config.h to
compromise vm_configurations.c

Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2020-10-30 20:24:28 +08:00
Yang, Yu-chu fc5add8dd6 acrn-config: add functions to get pci count per vm
Function to get pci dev number per VM

Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2020-10-30 20:24:28 +08:00
Yang,Yu-chu bda53a3599 acrn-config: Add functionality to find unused vbar base
Allocate unused vbar for SOS and pre-launched VMs.

- For SOS, find unused vbar in the range which is assigned to pci host
bridge. The allocated vbar cannot have confilicts with any existing pci devices
- For pre-launched VMs, find unused vbar in the range 0x80000000 to
0xfffffff. The alloacted vbar cannot have confilicts with any
passthrough devices and mmio.

Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2020-10-30 20:24:28 +08:00
Shuang Zheng b23374ccc9 acrn-config: get PTCT table from native environment
automatically get PTCT table from native environment for the usage
of pre-launched VMs.

Tracked-On: #5418

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:39:59 +08:00
Shuang Zheng 0e9775f4a4 acrn-config: integrate PTCT table for pre-launched RTVM
fill physical PTCT table into pre-launched vACPI table when PSRAM
is configured to passthrough to pre-launched RTVM.

Tracked-On: #5418

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:39:59 +08:00
Shuang Zheng faeef67c20 acrn-config: add PSRAM config in scenario setting
add CONFIG_PSRAM_ENABLED and CONFIG_PSRAM_PRE_RT_ENABLED config in
scenario setting and update Kconfig.

Tracked-On: #5418

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:39:59 +08:00
Shuang Zheng 6df069f6ba acrn-config: add PSRAM config in xmls
add PSRAM configs in xmls, only enable PSRAM and passthrough to
pre-launched RTVM for hybrid_rt scenario on tgl-rvp board.

Tracked-On: #5418

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:39:59 +08:00
Shuang Zheng c348cad1ee acrn-config: add mutually exclusive logic for legacy vuart and PCI vuart on config UI
Config tool UI will do mutually exclusive check the legacy vuart 0/1 and
PCI vuart 0/1 to make sure there is no legacy vuart and PCI vuart are
used at the same time for VMs.

Tracked-On: #5394

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:25:57 +08:00
Shuang Zheng 4f5885c271 acrn-config: add PCI VUART config in launch config UI
Add PCI VUART config for post-launched VMs in launch config UI. Users
can configure the console_vuart, configure or dynamically add or remove
communication_vuart based on the communication vuarts which are configured
from the scenario xml.

Tracked-On: #5394

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:25:57 +08:00
Shuang Zheng 788f28035d acrn-config: add PCI VUART config in scenario config UI
Add PCI VUART dynamic config for VMs in scenario config UI, keep legacy
VUART config. PCI vuart base can be set to INVALID_PCI_BASE and PCI_VUART;
users will configure the target_vm_id and target_vuart_id when PCI vuart
base is set to PCI_VUART; users can dynamically add or delete PCI vuart
for VMs.

Tracked-On: #5394

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-30 18:25:57 +08:00
Peter Fang d55dd1c0b9 OVMF release v2.3
- Explicitly reserve memory regions based on the input E820 map
- Revert "ovmf: reserve e820 table for PTCM"

Tracked-On: #5442
Signed-off-by: Peter Fang <peter.fang@intel.com>
2020-10-30 15:45:31 +08:00
Li Fei1 460124f984 dm: e820: refine e820 layout
We don't reserve PCI MMIO in e820 Table, it's included in DSDT ACPI Table.
About 0xA0000 - 0x100000 entry, we don't have any ACPI Table touch this region.
So we could remove it too.

After this change, we could only pass the reserved e820 table which we must
reserve to OVMF. In this case, the OVMF could trust ACRN-DM and pass the
reserved e820 table to guest instead of dropping it.

This patch needs the corresponding modify in OVMF. Otherwise, the guest could
not boot.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-30 15:45:31 +08:00
David B. Kinder bb6b226c86 doc: fix doxygen 1.8.17 issues
The new (1.8.17) release of doxygen is complaining about errors in the
doxygen comments that were's reported by our current 1.8.13 release.
Let's fix these now. In a separate PR we'll also update some
configuration settings that will be obsolete, in preparation for moving
to this newer version.

[External_System_ID]ACRN-6774

Tracked-On: #5385

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-10-29 08:25:01 -07:00
Jian Jun Chen ac8e0d6d10 hv: add BAR GPA for vmsix over msi in pre-launched vm
In pre-launched VM the GPA of vmsix BAR which is used for vmsix
over msi is calculated/allocated by acrn-config tool. The GPA
needs to be assigned to vdev when vdev is initialized. The
assignment is only needed for pre-launched VM. For SOS kernel
will reprogram the Bar base when startup. For post-launched VM
the Bar GPA will be assigned by device model via hypercall.

Tracked-On: #5316
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-29 16:12:12 +08:00
Jian Jun Chen 182620535b hv: use pci_vdev_write_vbar instead of vdev_pt_write_vbar
When init_vmsix_on_msi is called during the initialization of a pt
device, the vmsix bar used for vmsix over msi is just created. No
mapping/unmapping is done and pci_vdev_write_vbar should be called
instead of vdev_pt_write_vbar at the time. Currently the Bar mapping
is delayed till OS sizing the Bar. Backup vbar base_gpa to mmio_gpa
is not required here becuase it will be done later when Bar mapping.

Tracked-On: #5316
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-29 16:12:12 +08:00
Victor Sun a4cca45bc6 acrn-config: minor change scenario xml for ehl
changes:
	1. Change SOS VM rootfs to nvme0;
	2. Change hybrid_rt scenario VM0 mem size to 1GB;

Tracked-On: #5238

Signed-off-by: Victor Sun <victor.sun@intel.com>
2020-10-29 13:37:03 +08:00
Peter Fang 654d0f9d00 misc: life_mngr: use the entire read buffer for the SOS socket
The messages from the SOS socket can be safely read into the entire read
buffer.

Tracked-On: #5429
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-29 10:11:25 +08:00
Peter Fang 830b7749de dm: correctly handle EAGAIN in pm_vuart when listening
pm_vuart stops listening and relays the message right away if it
encounters EAGAIN during read(). This causes the messages relayed to be
fragmented.

Only relay the message when it encounters a null character or a newline
character, or when the buffer is full.

Tracked-On: #5429
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-29 10:11:25 +08:00
Zide Chen a776ccca94 hv: don't need to save boot context
- Since de-privilege boot is removed, we no longer need to save boot
  context in boot time.
- cpu_primary_start_64 is not an entry for ACRN hypervisor any more,
  and can be removed.

Tracked-On: #5197
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2020-10-29 10:05:05 +08:00
Shuang Zheng 2309cadc9a acrn-config: passthrough embeded tsn device for pre-launched RTVM
passthrough embeded tsn device for pre-launched RTVM on hybrid-rt
scenario of tgl-rvp board.

Tracked-On: #5427

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-29 09:47:21 +08:00
Shuang Zheng 5229c576d3 acrn-config: update tgl board xml with tsn IFWI
update tgl-rvp.xml for tgl boards with IFWI of tsn version to enable
the embeded tsn device.

Tracked-On: #5427

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
2020-10-29 09:47:21 +08:00
Yang, Yu-chu d743aa9b42 acrn-config: Get vbar base and index for vmsix supported devices
Add functionality to get free vbar base for the vmsix devices.

- The devices size is 4k.
- The mmio range for non SOS VM is 2G to 4G
- The mmio range for SOS is depended on the range which is assigned to
PCI bus hostbridge
- The next vbar index is based on last device vbar index vbar_i

Tracked-On: #5422
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2020-10-29 09:45:30 +08:00
David B. Kinder ec731bac0f doc: update doxygen configuration
Update some configuration settings that will be obsolete in the new
(1.8.17) doxygen release.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-10-26 09:20:50 -07:00
Shiqing Gao c51a96a11b doc: update coding guidelines
- add a rule for "U" suffix
 - release the restrictions about function documentation

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2020-10-26 09:20:18 -07:00
Yonghua Huang 30bbfa0d26 dm: confiure msix bar for hv-land ivshmem devices
This patch configures MSIX entry table bar for hv-land ivhsmem devices.

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang 9b4ba19753 hv: enable doorbell for hv-land ivshmem device
This patch enables doorbell feature for hv-land
ivshmem device to support interrupt notification
between VMs that use inter-VM(ivshmem) devices.

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang 62a36ce34b doc: update 'hv-virt-interrupt.rst'
Update this file as 'vlapic_intr_msi()' is renamed.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang 3ea1ae1e11 hv: refine msi interrupt injection functions
1. refine the prototype of 'inject_msi_lapic_pt()'
 2. rename below function:
    - rename 'vlapic_intr_msi()' to 'vlapic_inject_msi()'
    - rename 'inject_msi_lapic_pt()' to
      'inject_msi_for_lapic_pt()'
    - rename 'inject_msi_lapic_virt()' to
      'inject_msi_for_non_lapic_pt()'

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang 012927d0bd hv: move function 'inject_msi_lapic_pt()' to vlapic.c
This function can be used by other modules instead of hypercall
 handling only, hence move it to vlapic.c

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang f511a71c4e hv: add vmsix capability for hv-land ivshmem device
This patch exposes vmsix capability for ivshmem
  device:
  - Initialize vmsix capability in ivshmem PCI
    config space.
  - Expose BAR1 as vmsix entry table bar.

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang 8137e49e17 hv: add functions to initialize vmsix capability
- add 'vpci_add_capability()' to initialize one
   PCI capability in config space.
 - add 'add_vmsix_capability()' to add vmsix capability.

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00
Yonghua Huang cdfc82f03b hv: refine pass-thru device specific vmsix function
- write_vmsix_cap_reg(): emulates vmsix cap writes.
   write_pt_vmsix_cap_reg(): emulates msix cap write
   for PT devices.

 - rw_vmsix_table(): emulates vmsix table bar space access.

 - vmsix_handle_table_mmio_access(): emulates the vmsix
   bar space access only.

 - pt_vmsix_handle_table_mmio_access(): emulates the vmsix
   bar space access and remap msi entry for PT device if
   write operation is executed.

 - rename 'init_vmsix()' and 'deinit_vmsix()' to
   'init_vmsix_pt()' and 'deinit_vmsix_pt()' respectively,
   they're for PT devices only.

  - remove below 2 functions,call
        'pci_vdev_read_vcfg()' directly in cases they're used.
        - 'read_vmsi_cap_reg()'
        - 'read_vmsix_cap_reg()'

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Done <eddie.dong@intel.com>
2020-10-26 08:44:13 +08:00