Commit Graph

1710 Commits

Author SHA1 Message Date
Jason Chen CJ a87757d602 uefi: remove old interrupt injection method
we added uefi stub for hv, and want vm0 continue running under uefi env to
boot other uefi payload (osloader or bzImage).

during this, the uefi timer irq need be handled elegantly.

there are 3 types for uefi timer:
1. 8254 based on IRQ0 of PIC
2. HPET based on IOAPIC
3. HPET based on MSI

currently, we only support type 3 (HPET+MSI). But we are following a
in-correct flow to handle this timer interrupt:
- we set VMX_ENTRY_INT_INFO_FIELD directly if a timer interrupt happened
  before vcpu launching, this will make its vlapic mess up, which finally
  cause hpet timer stop.

this patch remove this in-correct approach, the new approach patch will
be followed by next patch.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:37 +08:00
Mingqiang Chi 2deb4cb458 mmu: Rename several variables related to page table type
rename 'PT_HOST' to 'PTT_HOST'
rename 'PT_EPT' to 'PTT_EPT'
rename 'ept_type' to 'table_type'

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:37 +08:00
Zheng, Gen 124910ba14 vm load: fix bug in loading kernel
According to the explaination for pref_address
in Documentation/x86/boot.txt, a relocating bootloader
should attempt to load kernel at pref_address if possible.
But due to a non-relocatable kernel will unconditionally
move itself and to run at perf address, no need to copy
kernel to perf_address by bootloader.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:37 +08:00
Minggui Cao 119b038551 to support firmware & ramdisk as multiboot mods
1. refine multiboot related code, move to /boot.
2. firmware files and ramdisk can be stitched in iasImage;
and they will be loaded as multiboot modules.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
2018-05-15 17:19:37 +08:00
Mingqiang Chi 35f5eef658 Add page mask MACRO
Add 'CPU_PAGE_MASK' used for calculate address,
Change IA32E_REF_MASK from 0x7ffffffffffff000 to 0x000ffffffffff000
for MMU/EPT entry, bit62:52(ignore) bit63(VE/XD)
if we want to obtain the address from the MMU/EPT entry,need to clear
bit63:52 by IA32E_REF_MASK

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:37 +08:00
Li, Fei1 74e2bfc15f Simple get_vmx_cap()
Don't check MSR Control Features in get_vmx_cap

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:36 +08:00
Mingqiang Chi cc1d532131 add data structure in vm for enable trusty feature
add key info structure
add sworld_eptp in vm structure, and rename ept->nworld_eptp
add secure world control structure

Change-Id:
Tracked-On:220921
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:36 +08:00
Yin Fengwei 189329e0de apicv: cancel event injection if vcpu is scheduled out
And re-inject the event after vcpu is scheduled in.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-05-15 17:19:36 +08:00
David B. Kinder e06947576f doc: update param spelling from VM to vm
doxygen comments for @param VM must match the actual parameter name vm
(lowercase)

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-11 14:44:28 +08:00
Eddie Dong 7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00