The port 0x64 is the status register of i8042 keyboard controller. When
i8042 is defined as ACPI PnP device in BIOS, enforce returning 0xff in
read handler would cause infinite loop when booting SOS VM, so expose
the physical port read in this case;
Tracked-On: #4228
Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
In current architecutre, the maximum vCPUs number per VM could not
exceed the pCPUs number. Given the MAX_PCPU_NUM macro is provided
in board configurations, so remove the MAX_VCPUS_PER_VM from Kconfig
and add a macro of MAX_VCPUS_PER_VM to reference MAX_PCPU_NUM directly.
Tracked-On: #4230
Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
The macro definition is changed in hypervisor code, so modify acrn-config
side accordingly.
Tracked-On: #4230
Signed-off-by: Victor Sun <victor.sun@intel.com>
rename the macro since MAX_PCPU_NUM could be parsed from board file and
it is not a configurable item anymore.
Tracked-On: #4230
Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
SOS vm only support legacy serial port emulation, so we need to
hide non-legacy serial ports from webUI when user want to select
serial port as SOS console.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. unify get_vuart_info_id/get_vuart_id api in board/scenario/launch
config tool.
2. if vm use 'vuart1(tty)' method to power off, make sure this vm have
select the vuart1 'SOS_COM2_BASE'.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add pm_channel support to parse and get 'poweroff_channel' item value
from launch config files, these values are selectable by user.
Tracked-On: #4212
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Some vm need power off method, so modify 'poweroff_channel'
item in the launch config files that user could select them from webUI.
Tracked-On: #4212
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. Some vm need mediator of 'virtio-console', so add 'console' item
into 'virtio_devices' leaf that user could edit them from webUI.
2. Add 'vuart0' item to enable/disable serial console emulation by
device model.
Tracked-On: #4186
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add virtio-console mediator support to parse and get 'virtio-console' item value
from launch config files, these values are editable by user.
Tracked-On: #4186
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
remove 'guest_init_pml4' and 'tmp_pg_array' in vm_arch
since they are not used.
Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
The initialization of "dmar_unit->gcmd" shall be done via reading from
Global Status Register rather than Global Command Register.
Rationale:
According to Chapter 10.4.4 Global Command Register in VT-d spec, Global Command
Register is a write-only register to control remapping hardware.
Global Status Register is the corresponding read-only register to report remapping
hardware status.
Tracked-On: #1842
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This patch fixes an issue with generation of guest ve820 when the size
of the memory is >512MB. The issue is primarily with respect to converting
between hex and int.
Tracked-On: #4219
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Now the GVT already tries to reserve the region.
the problem is that the region should be
reflected in PCI BUS0 memlimit32 and updated to DSDT table.
As the GVT PCI bar0/2 is in reserved region
and not updated to memlimit32 in DSDT table,
the problem is triggered.
Tracked-On: projectacrn#4227
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
"9e9e1f61 acrntrace: Add opt to specify the cpus where we should capture the data"
uses APIs of libnuma. So this patch adds dependency of libnuma in building-from-source.rst.
libnuma functions have been included in os-core-dev bundle of clearlinux.
Tracked-On: #4175
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
The BOARD and SCENARIO parameter of make hypervisor might be overridden
by menuconfig file or BOARD/SCENARIO XML files in make process, also the
$(BOARD)_acpi_info.h would be involved in build if exist, but user might
not be aware of that because the message could be easily ignored from
flooding logs. So give the configuration summary at the end of hypervisor
build process would be helpful for end user.
Tracked-On: #3779
Signed-off-by: Victor Sun <victor.sun@intel.com>
The patch adds acrn-config tool support for adding
non-continguous HPA allocations for pre-launched VMs
in hybrid scenario.
Tracked-On: #4217
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
For now, we set NOOP scheduler as default. User can choose IORR scheduler as needed.
Tracked-On: #4178
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Add yield support for schedule, which can give up pcpu proactively.
Tracked-On: #4178
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Implement .sleep/.wake/.pick_next of sched_iorr.
In .pick_next, we count current object's timeslice and pick the next
avaiable one. The policy is
1) get the first item in runqueue firstly
2) if object picked has no time_cycles, replenish it pick this one
3) At least take one idle sched object if we have no runnable object
after step 1) and 2)
In .wake, we start the tick if we have more than one active
thread_object in runqueue. In .sleep, stop the tick timer if necessary.
Tracked-On: #4178
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
sched_control is per-pcpu, each sched_control has a tick timer running
periodically. Every period called a tick. In tick handler, we do
1) compute left timeslice of current thread_object if it's not the idle
2) make a schedule request if current thread_object run out of timeslice
For runqueue maintaining, we will keep objects which has timeslice in
the front of runqueue and the ones get new replenished in tail.
Tracked-On: #4178
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
We set timeslice to 10ms as default, and set tick interval to 1ms.
When init sched_iorr scheduler, we init a periodic timer as the tick and
init the runqueue to maintain objects in the sched_control. Destroy
the timer in deinit.
Tracked-On: #4178
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
IO sensitive Round-robin scheduler aim to schedule threads with
round-robin policy. Meanwhile, we also enhance it with some fairness
configuration, such as thread will be scheduled out without properly
timeslice. IO request on thread will be handled in high priority.
This patch only add a skeleton for the sched_iorr scheduler.
Tracked-On: #4178
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
The calculation of the end boundry address is corrected by
adding the size extracted from _DYNAMIC to start address
in type of uint8_t while improving the code by calulating
the end boundry address after scanning, also reducing type
casts accordingly.
Tracked-On: projectacrn#4191
Signed-off-by: Gary <gordon.king@intel.com>
Normally, we care more about the current trace data than
buffered old data. So, this patch set FLAG_CLEAR_BUF by
default and adds one new option '-r' to unset the FLAG_CLEAR_BUF
if we want to capture the buffered old data.
---
v1 -> v2:
Add 'deprecated' mark to '-c' option
Tracked-On: #4175
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
This patch adds one new option '-a' to specify the cpus where we should
capture the trace data. If the this option is not set or set with wrong
optarg, we will capture the trace data of all possible cpus.
The set of the cpus can be specified as A,B,C, or A-C, or A,D-F, and so on.
Tracked-On: #4175
Acked-by: Yan, Like <like.yan@intel.com>
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
It is better to output it using float instead of int. Otherwise, we will
get '0 sec' for total run time if it is less than one second.
Tracked-On: #4175
Acked-by: Yan, Like <like.yan@intel.com>
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
The key in the list is unique. So, it is better to break the loop
when find the matching key instead of traversing the whole list.
Tracked-On: #4175
Acked-by: Yan, Like <like.yan@intel.com>
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Originally, we assume that the vmenter will sit at the first line
of the trace file. But if the vmexit comes earlier than vmenter.
The total vmexit cnt will be set as 0 by the first vmenter.
This patch fixes the issue by:
- Search the trace file to find the first vmexit entry and start to analyze here
and mark the TSC_BEGIN as the tsc of this vmexit.
- Inc the total vmexit cnt by 1 when meet the vmexit entry.
- Calc the vmexit duration when meet the vmenter in pair with the last vmexit.
Tracked-On: #4175
Acked-by: Yan, Like <like.yan@intel.com>
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
This is to make acrn config UI supports to edit more than one virtio
input devices in multi-lines.
Tracked-On: #4163
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Add the below flags, they are needed in -O2:
-fno-delete-null-pointer-checks:
* tells the compiler NOT to assume that null pointer deference does
not exist.
* Without this flag, below case cannot be detected:
a pointer might point to nullsometime during run-time and if there
is no validation for that pointer, it will cause the program to crash.
Since we don’t receive an error message saying that a pointer is
pointing to null, we will have a hard time trying to find the problem.
-fwrapv:
* tells the compiler that signed overflow always wraps.
* Without this flag, x + 10 > x will always be true for signed x.
With the flag, x + 10 > x is not always be true, as the overflow is
defined for x, and it could wrap.
Tracked-On: #4194
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
In APICv advanced mode, an targeted vCPU, running in non-root mode, may get outdated
TMR and EOI exit bitmap if another vCPU sends an interrupt to it if the trigger mode
of this interrupt has changed.
This patch try to kick vCPU off to let it get the latest TMR and EOI exit bitmap when
it enters non-root mode again if new coming interrupt trigger mode has changed. Then
fill the interrupt to PIR.
Tracked-On: #4200
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This patch updates kconfig to support server platforms
for increased number of VCPUs per VM and PT IRQ number.
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Tracked-On: #4196
This patch modifies the python scripts in scenario,
board and vm-configuration to support,
1. Generation of seperate ve820 for each VM.
2. Ability to configure each VM's HPA from
acrn-config UI tool.
3. Non-contiguous HPAs for pre-launched VMs.
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Tracked-On: #4195
Acked-by: Anthony Xu <anthony.xu@intel.com>
On some platforms, HPA regions for Virtual Machine can not be
contiguous because of E820 reserved type or PCI hole. In such
cases, pre-launched VMs need to be assigned non-contiguous memory
regions and this patch addresses it.
To keep things simple, current design has the following assumptions,
1. HPA2 always will be placed after HPA1
2. HPA1 and HPA2 don’t share a single ve820 entry.
(Create multiple entries if needed but not shared)
3. Only support 2 non-contiguous HPA regions (can extend
at a later point for multiple non-contiguous HPA)
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Tracked-On: #4195
Acked-by: Anthony Xu <anthony.xu@intel.com>
P-state scaling driver is present
There seems to be a corner case where target xml file
fails to get generated if there was no P-state scaling driver
or C-state idle driver present. This patch addresses it by
handling the file not present exception and setting a warning
as well a "not available" string to successfully generate
target xml file.
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Tracked-On: #4199
Acked-by: Victor Sun <victor.sun@intel.com>
To handle reboot requests from pre-launched VMs that don't have
GUEST_FLAG_HIGHEST_SEVERITY, we shutdown the target VM explicitly
other than ignoring them.
Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
If "make menuconfig" chooses hybrid or logical_partition scenario,
currently the build fails with "SCENARIO <$(SCENARIO)> is not supported.".
- CONFIG_LOGICAL_PARTITION: "awk -F "_|=" '{print $$2}'" yields the second
field (LOGICAL) only. The new "cut -d '_' -f 2-" keeps all fields after
"CONFIG_".
- Add the missing HYBRID scenario.
Tracked-On: #4067
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
1. Use acrn-configure tool to generate xml files to support TGL
RVP board. You need make menuconfig as guide in github, and then
comiple as following:
make hypervisor BOARD_FILE=path/xxx.xml SCENARIO_FILE=path/yyy.xml
2. Also uos launch script can be generated by acrn-configure tool with the
uos luanch xml file
Tracked-On: #4181
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Pre-launched or SOS VMs could use ramdisks to boot. This
patch adds acrn-config tool support to parse such use-case
scenario xmls.
Tracked-On: #4197
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch adds ramdisk_mod tag to all supported boards and
logical partition, hybrid, industry and sdc xmls
Tracked-On: #4197
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
ptirq_prepare_msix_remap was called no matter whether MSI/MSI-X was enabled or not
and it passed zero to input parameter virtual MSI/MSI-X data field to indicate
MSI/MSI-X was disabled. However, it barely did nothing on this case.
Now ptirq_prepare_msix_remap is called only when MSI/MSI-X is enabled. It doesn't
need to check whether MSI/MSI-X is enabled or not by checking virtual MSI/MSI-X
data field.
Tracked-On: #3475
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Do vMSI-X remap only when Mask Bit in Vector Control Register for MSI-X Table Entry
is unmask.
The previous implementation also has two issues:
1. It only check whether Message Control Register for MSI-X has been modified when
guest writes MSI-X CFG space at Message Control Register offset.
2. It doesn't really disable MSI-X when guest wants to disable MSI-X.
Tracked-On: #3475
Signed-off-by: Li Fei1 <fei1.li@intel.com>
1. disable physical MSI before writing the virtual MSI CFG space
2. do the remap_vmsi if the guest wants to enable MSI or update MSI address or data
3. disable INTx and enable MSI after step 2.
The previous Message Control check depends on the guest write MSI Message Control
Register at the offset of Message Control Register. However, the guest could access
this register at the offset of MSI Capability ID register. This patch remove this
constraint. Also, The previous implementation didn't really disable MSI when guest
wanted to disable MSI.
Tracked-On: #3475
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Need to enable gvt bar registration, so remove the previous workaround patch.
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The current design has the following problem:
uos kernel may update gvt bars' regions,
but ACRN-DM doesn't know this update.
ACRN-DM only know out-of-date gvt bar regions,
For simplicity, mark these bar regions as OOD bar regions.
uos kernel may allocate OOD bar regions for
other pci devices, which will result in ACRN-DM
bar regions inconsistency with uos kernel.
The new design is the following:
When other pci device update bar regions
(1) ACRN-DM updates gvt bars' regions
provided by a system file.
(2) ACRN-DM updates this pci device bar regions
v5 -> v6:
* add more comments
v4 -> v5:
* remove & for callback func assignment
v3 -> v4:
* compare gpu bar address to avoid unnecessary
* unregistered/registered operation
v2 -> v3:
* call unregister_bar and register_bar when update gvt bars
* update gvt reserved regions when update gvt bars
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Mingqiang Chi