Commit Graph

12 Commits

Author SHA1 Message Date
Huihuang Shi 91fdffb19a HV:debug:fix "signed/unsigned conversion without cast"
Misra C required signed/unsigned conversion with cast.

V1->V2:
  a.split patch to patch series

V2->V3:
  a.Change the API tgt_uart/ static int uart16550_get_rx_err(uint32_t rx_data) to return uint32_t
  b.modified the format of if from "if (length > 32*(length/32))" to
"if (length % 32U > 0)"

V3->V4:
  a.change the uint64_t type numeric constant's suffix from U to UL

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 12:18:38 +08:00
Junjie Mao aa505a28bb HV: treewide: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2018-06-21 13:12:39 +08:00
Huihuang Shi 23921384d0 HV:debug:fix "expression is not Boolean"
MISRA C explicit required expression should be boolean when
in branch statements (if,while...).

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-20 14:19:47 +08:00
David B. Kinder f4122d99c5 license: Replace license text with SPDX tag
Replace the BSD-3-Clause boiler plate license text with an SPDX tag.

Fixes: #189

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-06-01 10:43:06 +08:00
Zide Chen 8f16faab04 HV: further cleanup of header inclusions
According to the comments in hypervisor:
 " This file includes config header file "bsp_cfg.h" and other
	hypervisor used header files.
	It should be included in all the source files."

this patch includes all common header files in hypervisor.h
then removes other redundant inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Li, Fei1 edb26a7e17 hv: refine the left atomic operation
rename atomic_cmpxchg_int to atomic_cmpxchg
replace atomic_cmpset_long with atomic_cmpxchg64
rename atomic_readandclear_long to atomic_readandclear64

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 1f3da93e74 hv: refine atomic_load/store_xxx name
rename atomic_load/store_xxx32 to atomic_load/store
rename atomic_load/store_xxx64 to atomic_load64/store64

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 bd3f3b00f7 hv: fix incorrect use of atomic_set_xxx
1. vpic_wire_mode no need to atomically set its value.
2. uart open conut want to atomically set its value not atomically set
its bits.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Zheng, Gen c5f860e1cb MMU: bug fix on operating va <=> pa convertion
Before referencing to physical address of devs such as lapic, ioapic,
vtd, and uart, switch to virtual address.
Use a phisical address of pml4 to write CR3.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen d02f4d4a5f refine: change the address arguments type of mmio access api
Change the address arguments type of mmio access api from uint64_t
to void*.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen 6b1782b360 refine: remove redundant data type definition
remove data defination of mmio_addr_t, vaddr_t, paddr_t,
and ioport_t.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:54 +08:00
Eddie Dong 7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00