The access to PCI config_space is handled in HV for Passthrough pci
devices. And it also provides one mechanism to forward cfg_access of
some registers to DM. For example: the opregion reg for GPU device.
This patch tried to add the support of emulated PCI ROM bar for the
device. And it doesn't handle the phys PCI ROM bar of phys PCI devices.
At the same time the rom firmware is provided in DM and pci rom bar_reg
is also emulated in DM, this leverages the quirk mechanism so that the
access to PCI rom bar_reg is forwarded to DM.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
Add the option of "romfile=file_location" to specify the rom file for rombar
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
The pci_reg 0x30 of PCI config_space is used to check whether the PCI rom
bar is supported. When the PCI rom is supported for the device in guest vm,
the 0x30 pci_reg is emulated and it can return the addr/enable bit.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
PCI ROM is the firmware specific to PCI device and it is provided by
the device vendor. The PCI rom resides in 0x30 offset of PCI config space.
This can be used to check whether the PCI rom exists. And when it exists,
it can load the firmware from the addr that is obtained from ROM bar addr.
For the user-vm, it will try to load the rom_file for the given PCI device and
enable the VM to access the firmware that is defined in rom_file.
BTW: The emulated rom_file is converted from efi image by using EfiRom. It has
no dependency on the ROM bar of physical PCI devices. Of course if the physical
PCI devices supports the ROM bar, the rom_file can also be dumped from the PCI
rom.
Now this is limited to PCI display device.
V2->V3: Add the function of pci_load_rombar/pci_release_rombar to handle the
rombar in course of passthrough_init/deinit.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
Now the device model only supports the 0..5 PCI bar for PCI/PCIE devices.
This tries to allocate the PCI_MEM32 resource for PCI ROM bar.
V1->V2: Use the PCI_ROMBAR as bar index and PCIBAR_ROM bar type when calling
the pci_emul_alloc_bar to allocate the guest physical addr for PCI ROM bar.
And it will allocate the resource from PCIBAR_MEM32 region.
V2->V3: Add more comments that describes the parameter of pci_emul_alloc_bar.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
The application binary interface (ABI) is an important aspect of
hypercalls. But unfortunately it is not yet defined anywhere in the current
HLD.
This patch adds the current ABI specification to the hypercall section of
HLD.
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
With multiple xs:documentation nodes under the same xs:annotation, xs2js
will convert the XML into a dict where the key `xs:documentation` maps to a
list rather than a string. This patch enhances the converter.py to handle
such case properly.
Tracked-On: #8098
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Fix the bug in iothread handler, the event should be read out so that the
next epoll_wait not return directly as the fd can still readable.
Tracked-On: #8181
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The design of ACRN CPU performance management is to let hardware
do the autonomous frequency selection(or set to a fixed value),
and remove guest's ability to control CPU frequency.
This patch is to remove guest's ability to control CPU frequency by
removing the guests' HWP/EIST CPUIDs and blocking the related MSR
accesses. Including:
- Remove CPUID.06H:EAX[7..11] (HWP)
- Remove CPUID.01H:ECX[7] (EIST)
- Inject #GP(0) upon accesses to MSR_IA32_PM_ENABLE,
MSR_IA32_HWP_CAPABILITIES, MSR_IA32_HWP_REQUEST,
MSR_IA32_HWP_STATUS, MSR_IA32_HWP_INTERRUPT,
MSR_IA32_HWP_REQUEST_PKG
- Emulate MSR_IA32_PERF_CTL. Value written to MSR_IA32_PERF_CTL
is just stored for reading. This is like how the native
environment would behavior when EIST is disabled from BIOS.
- Emulate MSR_IA32_PERF_STATUS by filling it with base frequency
state. This is consistent with Windows, which displays current
frequency as base frequency when running in VM.
- Hide the IA32_MISC_ENABLE bit 16 (EIST enable) from guests.
This bit is dependent to CPUID.01H:ECX[7] according to SDM.
- Remove CPID.06H:ECX[0] (hardware coordination feedback)
- Inject #GP(0) upon accesses to IA32_MPERF, IA32_APERF
Also DM do not need to generate _PSS/_PPC for post-launched VMs
anymore. This is done by letting hypercall HC_PM_GET_CPU_STATE sub
command ACRN_PMCMD_GET_PX_CNT and ACRN_PMCMD_GET_PX_DATA return (-1).
Tracked-On: #8168
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reset the real_time_vcpu to 'n' if the VM is not a real-time VM.
Tracked-On: #8145
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
HPET is used to calibrate the tsc frequency if system fails to
get the accurate frequency from CPUID 0x15. But on some platforms
(for example: the emulated ACRN on QEMU) HPET is not started
by default, which causes the failure of calibration TSC by HPET.
Tracked-On: #8113
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
The ACRN Configurator release 3.1 following the release 3.0 logic, so
the COM2 still used for S5.
This patch modify the "The release v3.0 ACRN Configurator assigns… …"
to "The release v3.0+ ACRN Configurator assigns… …" and refine a typo
issue.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The BDF of user setting should skip the slot '00', '01', '02', '1f', all
these slots should select one of the 03~1e.
This patch add an assertion to check the above policy.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
1. In the title "Create a new Scenario", capitalize the "N" in "new".
2. Fix the file path to the installer.
Tracked-On: #8137
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
to avoid misleading for users, delete the description about
hypervisor relocation disabling, since it is not officially
supported by ACRN configurator now.
Tracked-On: #8133
Signed-off-by: hangliu1 <hang1.liu@linux.intel.com>
the configurator can clear its corresponding I/O port or BDF settings automatically when the VM of a vUART endpoint changes
v1-->v2: support the result working on multiple VUART Connections
Tracked-On: #8033
Signed-off-by: Chuang-Ke <chuangx.ke@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Now, if you use a memory address below 4G, there will be a warning,
but the build process of the hypervisor will not be interrupted.
Tracked-On: #6690
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
improve the translateError function by adding a condition: if there are errors describing the same error and same paths, remove the repeat one.
Tracked-On: #8117
Signed-off-by: Chuang-Ke <chuangx.ke@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
There is some issue when use upgrade to update some old xml version to
release_3.1, this patch modify the upgrade script to fix these issue.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Because of the iteration of i as is, the condition i <= XHCI_MAX_DEVS
always results as true and thus is unnecessary.
When compiling with cflag -Werror this condition will result in a
compilation failure.
Tracked-On: #8114
Signed-off-by: Marius Rodi <marius.rodi@linutronix.de>
The current code have not check whether all cache region has "Code and
Data Prioritization", it's an issue for some platform which have only
L2 or L3 "Code and Data Prioritization" capability.
This patch add assertion to check whether all L2, L3 cache could be set
CDP_ENABLE.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Restore a hidden option and its type accidentally removed by PR #8100 and #8099
Tracked-On: #8098
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Commit 2a8b80d0c ("config_tools: board_inspector: guess L3 CAT parameters
if not reported via CPUID") refactors the implementation of `--add-llc-cat`
option of the board inspector but does not update the referenced XML nodes
properly. This patch fixes a using-undefined-variable issue introduced by
that commit.
Tracked-On: #7948
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Generate config_summary.py script in misc/config-tools/scenario_config
directory. This script can extract important information from scenario
and board xml to summary it into RST format text.
Tracked-On: #8063
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
The configurator build requires the released documentation to be
published before it normally would so it can resolve :ref: links in
tooltips. Move these :ref: links into a second xs:documentation tag so
the reference will appear in the option documentation but not in the
tooltip (and break this premature dependency in the configurator build).
Tracked-On: #8098
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
zhangrouyu