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doc: Minor edit to RDT tutorial 

Signed-off-by: Reyes, Amy <amy.reyes@intel.com>
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Reyes, Amy 2022-09-14 12:09:16 -07:00 committed by Amy Reyes
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12
doc/tutorials/rdt_configuration.rst
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@ -164,12 +164,12 @@ The table title shows important information:
The above example shows an L2 cache table. VMs assigned to any CPU cores 2-6 can
have cache allocated to them.
The table's columns show the names of all VMs that are assigned to the CPU cores
noted in the table title, as well as their vCPU IDs. The table categorizes the
vCPUs as either standard or real-time. The real-time vCPUs are those that are
set as real-time in the VM's parameters. All other vCPUs are considered
standard. The above example shows one real-time vCPU (VM1 vCPU 2) and two
standard vCPUs (VM0 vCPU 2 and 6).
The table's left-most column shows the names of all VMs that are assigned to the
CPU cores noted in the table title, as well as their vCPU IDs. The table
categorizes the vCPUs as either standard or real-time. The real-time vCPUs are
those that are set as real-time in the VM's parameters. All other vCPUs are
considered standard. The above example shows one real-time vCPU (VM1 vCPU 2) and
two standard vCPUs (VM0 vCPU 2 and 6).
.. note::