There are many quirks in Intel xHCI implementation and it is very hard
to debug under Microsoft Windows OS, hence use ACRN xHCI extented
capabilities as the default setting.
Tracked-On: #3163
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
There has one new DRD driver followed usb role framework which is just
upstreamed to Linux community. This patch updates the xHCI DM to be
compatible with it. DM DRD code follows DRD spec to implement and make
it more reasonable.
Signed-off-by: Liang Yang <liang3.yang@intel.com>
Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
For dedicated xHCI extended capability, it need set corresponding PCI VID/PID.
This patch sets the Intel Apollo Lake platform PCI VID/PID for DRD
capability which will be checked for enabling DRD fucntion in new DRD
driver. Besides, this patch refines the PCI VID/PID related code.
Signed-off-by: Liang Yang <liang3.yang@intel.com>
Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This patch implements Intel ApolloLake xHCI extended capabilities. It
includes two dual role switch registers for switching shared
USB2&USB3 phys between xHCI and xDCI.
Change-Id: I2533537d8a4224da3cf9b2e7475aab9f65347a4a
Signed-off-by: Liang Yang <liang3.yang@intel.com>
Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Every platform should have their own xHCI specific extended
capabilities, but the current xHCI DM is not scalable for them. This
patch refines related logic to make it scalable.
Current code only support 4 registers(4*32) as basic extended
capabilites. Base on this new implementation, the mmio range from
excapoff to regsend will cover real excap size according to the cap
parameter.
Change-Id: Ic55a4494e090ec255939cdb8f32950e3c8a66082
Signed-off-by: Liang Yang <liang3.yang@intel.com>
Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Xiaoguang Wu