When one single device being connected after multiple-levels of PCI-to-PCI
bridges, all those bridges may have the same MMIO window. That causes the
current static allocator not to consider that window being occupied because
of how it detects nested MMIO regions.
Remove duplicates in the list of secondary bus MMIO windows to fix that
issue.
Tracked-On: #8312
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The offline tool use a utility libary and use "common" to named it, this
name conflict with some customer's local library, so we rename it to a
better and clear name.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Prevent allocator to allocate PCI bus mmio windows to other devices.
Tracked-On: #8191
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Modified the copyright year range in code, and corrected "int32_tel"
into "Intel" in two "hypervisor/include/debug/profiling.h" and
"hypervisor/include/debug/profiling_internal.h".
Tracked-On: #7559
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
The current code can't config PCI vUART by a unified HV Config and there
is a conflict between the HV vUART Config and PCI vUART Config.
This patch use PCI vUART Config to replace the HV vUART Config when the
vUART connection type is PCI and modify the launch scenario to make sure
the BDF is correct when user launch post launched VMs.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
The GPA SSRAM area size in pre-launched VMs was hard-coded to 8MB.
Since this area is mapped from host SSRAM area, it will cause compile
problem when host's SSRAM area is larger than 8MB.
To solve this issue, we have to calculate SSRAM area's size in
gpa.py, and generate a macro PRE_RTVM_SW_SRAM_MAX_SIZE for HV
to use.
PRE_RTVM_SW_SRAM_START_GPA/END_GPA can be calculated by end/size
in HV, so they are removed.
When SSRAM is not configured in the system, PRE_RTVM_SW_SRAM_MAX_SIZE
is set to 0.
Crl_bin is not needed in guest. So it's size is removed in bin_gen.py.
Tracked-On: #7212
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
This patch includes:
1.add load_order(PRE_LAUNCHED_VM/SERVICE_VM/POST_LAUNCHED_VM) parameter
2.change vm_type parameter to values as RTVM, STANDARD_VM, TEE, REE
TEE and REE are hide in UI.
3.deduce vm severity in vm_configuration from vm_type and load_order
This patch not includes:
change for scenario_config and functions called by scenario_config about checking
v2->v3:
*Refine template load_order
v1->v2:
*Change variable name from vm_type to load_order
*Change LoadOptionType to LoadOrderType
*Change VMOptionsType to VMType
*Add TEE_VM/REE_VM description
*Refine acrn:is-pre-launched-vm
Tracked-On: #6690
Signed-off-by: hangliu1 <hang1.liu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
According to the new design of DX, implement ivshmem configuration
and generate hv related files.
Tracked-On: #6690
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Not all pci hostbridge has a device on it. Remove the logic which
assumes there is at least one device.
Tracked-On: #7077
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
The pre-rtvm uses the RTCT tab to determine it's SSRAM address.
It was origionally duplicated from the host, and keeped its address
and layout.
To move the SSRAM area in ve820, we have to modify the guest's RTCT
tab first.
This patch uses the board_inspector's RTCT module to parse the host's
RTCT tab, and calculate the offset, then modifies the SSRAM/bin enties,
and saves it to the new RTCT bin file.
Tracked-On: #6674
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Rename SOS_VM type to SERVICE_VM
rename UOS to User VM in XML description
rename uos_thread_pid to user_vm_thread_pid
rename devname_uos to devname_user_vm
rename uosid to user_vmid
rename UOS_ACK to USER_VM_ACK
rename SOS_VM_CONFIG_CPU_AFFINITY to SERVICE_VM_CONFIG_CPU_AFFINITY
rename SOS_COM to SERVICE_VM_COM
rename SOS_UART1_VALID_NUM" to SERVICE_VM_UART1_VALID_NUM
rename SOS_BOOTARGS_DIFF to SERVICE_VM_BOOTARGS_DIFF
rename uos to user_vm in launch script and xml
Tracked-On: #6744
Signed-off-by: Liu Long <long.liu@linux.intel.com>
Reviewed-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
If a legacy vuart base is configured as "CONFIG_COM_BASE", allocate a
base with unused io-port address with length 0x10.
The post-launched VM's unused io-port address range is [0xD00, 0xFFFF].
The pre-launched VM's unused io-port address range is [0xD00, 0xFFFF]
but the passthrough devices' io-port address are reserved.
The SOS VM's unused io-port address range is [0xD00, 0xFFFF] but any
native devices' io-port address are reserved. However, the io-port
address which is passed through to any pre-launched is reusable.
Tracked-On: #6652
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Pass through the io-ports for the passthrough pci devices of
pre-launched VM.
Three parts to support this feature:
1. Identical map the pci devices io-port address for pre-launched VM
2. Set the io-ports address range to DSDT
3. Avoid to allocate the bar index for VMSIX
Tracked-On: #6620
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
The term PSRAM is now obsoleted and should be replaced with SSRAM, as has been
done by commit 9facbb43b3 ("config-tool: rename PSRAM to SSRAM"). However,
there are two places in the configuration toolset that still uses PSRAM. This
patch updates these missed occurrences accordingly.
Tracked-On: #6012
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
If passthrough TPM2 is enabled and the log area is present, allocates
the log_area_start_address with the size log_area_minimum_length(256K).
Tracked-On: #6320
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
It is a common practice to parse PCI BDF in the static allocators. This
patch moves the BusDevFunc class (which is a named tuple encoding a BDF) to
lib.py and uses it for BDF parsing throughout the static allocators.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds interrupt pin related information into the board XML,
including:
* The PCI routing table in ACPI DSDT/SSDT are parsed and generated into
the board XML as "interrupt_pin_routing" nodes.
* IRQs encoded in _CRS directly are represented as resources of type
"irq".
* Interrupt lines (i.e. INTx#) of PCI devices are represented as
resources of type "interrupt_pin". When the PCI routing table is
available, the corresponding interrupt line is identified and
represented as the "source" attribute of the resource node.
Due to the existence of vIOAPIC in ACRN VMs, the board inspector interprets
the \_PIC method with parameter 1 to inform the ACPI namespace that the
interrupt model should be in APIC mode.
v1 -> v2:
* Remove the msi_enable variable which is defined but never used.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
A vmsix supported passthrough device expects the first unused bar region
for vmsix. Pop the first unused_bar_index in gpa.py instead.
Reference code: init_vmsix_on_msi of hypervisor\dm\vpci\vmsix_on_msi.c
Tracked-On: #6192
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Add methods allocates the mmio bar base to console vuart,
communication vuarts, inter-vm shared memory and passthrough pci
devices.
For SOS:
- get low mem by parsing board xml.
- get high mem by parsing board xml, if the high mem is not enabled,
the high mem start address would be ~0UL and the end address is 0UL
- get the occupied mmio windows by parsing board.xml
- for each console vuart, communication vuart and inter-vm shared memory
devices, assign unused mmio windows to them
- all the assigned mmio windows must be unique and should not overlay
with any devices' mmio window
- the passthrough devices mmio windows can be reused in SOS vm
- each allocated mmio start address must be 4k alignment if the length
of bar is smaller than 4k
- each allocated mmio start address must be aligned with the bar length
if its length is greater than 4k
- the 32bits bar will fall in low mem range only
- 64bits bar will look for free mmio in low mem rage first, if the high
mem is enabled, the 64bits bar will look for free mmio in high mem
range if there is not enough space in low mem range
- allocator raises an error if there is not enough mmio space
For pre-launched VM:
- the high mem range is [256G, 512G)
- the low mem range is [2G, 3.5G)
- there is no used mmio window initially
- for each console vuart, communication vuart, inter-vm shared memory
devices and passthrough devices, assign unused mmio windows to them
- all the assigned mmio windows must be unique and should not overlay
with any devices' mmio window
- the 32bits bar will fall in low mem range only
- 64bits bar will look for free mmio in low mem rage first and then
look for free mmio in high mem range if there is not enough space in
low mem range
- each allocated mmio start address must be 4k alignment if the length
of bar is smaller than 4k
- each allocated mmio start address must be aligned with the bar length
if its lenght is greater than 4k
- allocator raises an error if there is not enough mmio space
Tracked-On: #6024
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This patch adds support to parse RTCT v2 using the refined board XML
schema. The major changes include:
- Add the RTCT v2 parser in the acpiparser module. The version of an RTCT
is detected automatically to choose the right parser.
- Extract software SRAM capabilities of caches into the board XML.
- Move the logic that determines the software SRAM base address for the
pre-launched VM to the static allocator of GPAs.
- Generate software SRAM related macros into misc_cfg.h when necessary.
Tracked-On: #6020
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Junjie Mao