GUEST_FLAG_STATELESS indicates guest is running a stateless operating
system and need to be shutdown forcefully without data loss. This flag
is only appalicable to pre-launched VM. For TEE_VM, this flag will be
set implicitly.
Tracked-On: #8671
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This patch is to change the vUART resource occupied by S5 function
between Service VM and guest VM to avoid the standard UART port
conflict when legacy UART passthrough to guest VM.
Tracked-On: #8622
Signed-off-by: YuanXin-Intel <xin.yuan@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Jian Jun Chen <jian.jun.chen@intel.com>
As ivshmem has switched from static allocation to E820 allocation,
the hv_ram_size no longer needs to include ivshmem size.
Tracked-On: #8522
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
In hv, we implement the feature of thermal virtualization,
We want to use this GUEST_FLAG_VTM flag to enable and
disable this feature. So we mark this flag in config
tools.
Tracked-On: #8595
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Signed-off-by: Zhangwei6 <wei6.zhang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Python 3.12 adds escape sequence check in strings, if it is invalid,
a SyntaxWarning will be given. Fix it by using raw string notation
in regular expressions, and changing comments in unused string literal
to normal comments.
Tracked-On: #8588
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Set GUEST_FLAG_VHWP guest flag for VMs who own pCPUs. Windows does not
manage CPU frequency in virtualized environment, so this flag is not set
for waag. Platforms without HWP capability should not have this flag
either.
Tracked-On: #8414
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
When one single device being connected after multiple-levels of PCI-to-PCI
bridges, all those bridges may have the same MMIO window. That causes the
current static allocator not to consider that window being occupied because
of how it detects nested MMIO regions.
Remove duplicates in the list of secondary bus MMIO windows to fix that
issue.
Tracked-On: #8312
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The offline tool use a utility libary and use "common" to named it, this
name conflict with some customer's local library, so we rename it to a
better and clear name.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The legacy logic use double IVSHMEM_SIZE to calculate the HV RAM, it can't
match the current code.
This patch use the IVSHMEM_SIZE size only.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
According to section 6.1.1, ACPI Spec 6.4, _ADR of a device object under
PCI/PCIe bus can use a special function number 0xFFFF to refer to all
functions of a certain device. Such objects will have their own nodes in
the board XML, and that causes build-time issues when a static allocator
attempts to get all BDFs occupied under the root bus because 0xFFFF is not
a valid function number (which ranges from 0 to 7).
This patch skips ACPI devices with such addresses when listing existing
BDFs.
Tracked-On: #8293
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The current code use VM number to calculate HV_RAM_SIZE, this is not
match the HV logic.
This patch use the max number of trusty VMs to calculate the size of
sworld memory and assume 4M ram / VM to calculate the final ACRN ram
size.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This patch is to generates frequency limits for each CPU, as a set of
data structure in hypervisor .c code.
With the frequency limits data, the hypervisor performance manager does
not have to deal with the CPU/board info. It just choose the
highest/lowest/guaranteed performance level and performance/nominal
p-state, and use them to construct HWP_REQUEST/PERF_CTL reg value.
How are frequency limits decided:
- For CPUs in standard VMs, frequency limits are just decided by
CPU/board info.
- For CPUs assigned to RTVMs, we want certainty in latency, so just
set its frequency to nominal/guaranteed by letting highest=lowest.
- In some cases, CPUs are sharing frequency on hardware level
(e.g. ADL e-cores in group of 4). This is described as _PSD in ACPI
spec, or 'frequency domain' in Linux cpufreq driver. Thoese CPUs'
frequency are linked together. If one of them are running RTVM,
all other CPUs in the domain should be set to the same frequency.
Tracked-On: #8168
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Prevent allocator to allocate PCI bus mmio windows to other devices.
Tracked-On: #8191
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Now, if you use a memory address below 4G, there will be a warning,
but the build process of the hypervisor will not be interrupted.
Tracked-On: #6690
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
The current code sort cpu list by string order, this is an issue when
we want to assign more then 10 vCPUs for some VM.
So this patch rewrite the sort of these list, now the cpu list order
by int type.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Add MAX_PCI_BUS_NUM in UI for user.
If user defined MAX_PCI_BUS_NUM is greater than the value
calculated by board.xml, use user defined MAX_PCI_BUS_NUM.
Tracked-On: #8018
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Fixed the problem that acrn can still build normally
when the memory addresses of HV and VM conflict, which
causes the hypervisor to hang.
At the same time, defined a class to process memory to
obtain and check the available memory range.
Memory range obtain and check related functions are
defined as class methods.
Tracked-On: #7913
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
Today users still need to manually copy the RTCT binary file when they want
to passthrough software SRAM to a pre-launched RTVM, which is far from
being user friendly.
To get rid of that step, this patch extracts all information from the RTCT
table and format them in the board XML which is the only file users need to
copy from their target platform to build the hypervisor. The patch that
immediately follows will then use such information to generate vRTCT for
the pre-launched VM.
A side effect of this change is that more ranges, which represents those
reported by RTCT such as the CRL binary or the error log area, will be
added to the `memory` section of the board XML. The `id` attributes of
those range will be used to identify what that range is for. As a result,
getting RAM of the physical platform from the board XML requires additional
conditions on the `id` attributes to avoid counting non-RAM regions
unintendedly.
Tracked-On: #7947
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Currently, on the whl-ipc-i5 platform, we found a warning message when
building ACRN with the shared scenario XML file from github.
However, this doesn't affect any feature of ACRN according to the QA's
test result.
So this patch removes this check in order not to confuse users at the first.
If necessary, we will add back the check after getting more detail.
v1-->v2
degrade the log level to debug.
Tracked-On: #7926
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Modified the copyright year range in code, and corrected "int32_tel"
into "Intel" in two "hypervisor/include/debug/profiling.h" and
"hypervisor/include/debug/profiling_internal.h".
Tracked-On: #7559
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
Fixed a logic error in one line of code in
misc/config_tools/static_allocators/memory_allocator.py.
Tracked-On: #7838
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
The current code can't config PCI vUART by a unified HV Config and there
is a conflict between the HV vUART Config and PCI vUART Config.
This patch use PCI vUART Config to replace the HV vUART Config when the
vUART connection type is PCI and modify the launch scenario to make sure
the BDF is correct when user launch post launched VMs.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
There were some legacy logic of the current code, the PCI vUART index
in the launch script have not count the vUART of S5 and life_mngr_win
use the COM2 as default vUART.
This patch change the vUART index and irq to adapt above logic and all
of these legacy code will be refine next version.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
update the hugepages algorithm as the following steps.
1. calculate the total hugepages of service vm using the formula.
"total memory*0.98 - the memory consumed by pre-launched VMs - 5G
-300M*num(number of virtio gpu instance)".
2. calculate hugepage 1G based post-launched vm memory setting.
3. check if the memory configured in post launch VMs is not larger than
the total hugepages.
Compared with the previous version, this patch removes the 2M hugepage
and the correction value, also update the formula of total hugepage.
Tracked-On: #7301
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
The current RDT class and interface was define by the clos.py which is
mix get and merge RDT policy, create clos nodes.
Now we need call these interface to check the CLOS IDs number after
merged RDT policy, so this patch abstract the RDT interface to common
and add an assert to check the CLOS IDs number.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
1.The memory allocation effect is tested under XML files on multiple platforms.
2.Modified the conversion of memory units during memory reading and processing (MB to Byte).
Tracked-On: #7730
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
The current code use a start address and hv_ram_size to find the start
address of acrn.bin, the start address is 32M which leaving too much
memory and will be load modules by grub, sometimes these modules will
override the HV log region.
This patch set the start address to 4M to avoid the above issue as much
as possible.
This algorithm depend on the board info, so the board XML should be
generate again if user change the SSRAM.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
The current code assume there was one Console vUART all the time, and
there is an issue when the Console vUART is None.
This patch add the case of "None" and add assert to check no serial
console config.
Tracked-On: #6690
Signed-off-by: Chenli Wei chenli.wei@intel.com
The current code assume that there must be an HV_RAM_START element in
the scenario and we will generate it if user have not set, the default
value of HV_RAM_START is 0x00400000 which cause an overlap issue.
This patch remove the requires of HV_RAM_START element, calculate
HV_RAM_SIZE and find a region of e820 to run the ACRN which start
address will be HV_RAM_START.
It is still valid if the user set HV_RAM_START by XMLs.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The current code use COM1 or COM2 for LPC and there is an conflict with
S5 feature.
This patch filter these COM Ports and fix the above issue.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The current code use cache type to check whether enable the CDP mode,
then merge policy by clos_mask, sometimes the data and code CLOS is not
continuous.
This patch add a special CDP policy to record and merge policy to fix
this above issue.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The current code use a merge interface to merge policy which fix match
and merge in one function.
This patch split the merge interface and add a match interface to check
whether this policy could be merged.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Add an explicit "None" entry in HV console selector if user would like
to disable debug console or there is no serial console available.
Tracked-On: #7546
Signed-off-by: Calvin Zhang <calvinzhang.cool@gmail.com>
Because SR-IOV is enabled to obtain board xml,
the xpath address cannot resolve the @address='0x20000' address.
cause the build to fail. fix build issues
Tracked-On: #7371
Signed-off-by: zhongzhenx.liu <zhongzhenx.liu@intel.com>
The legacy code get all non-stand vUARTs from scenario_etree and generate
the serial.conf, now we need add more non-stand vUARTs which was config
by offline tool and record by allocation_etree.
This patch add allocation_etree to the list, then add all non-stand
vUART to serial.conf which will config by SERVICE VM.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The current code align MAX_IR_ENTRIES with the roundup to 2^n of the
CONFIG_MAX_PT_IRQ_ENTRIES, there is an issue of the powerof2_roundup to
calculate the macro, and the code style is very ugly when we use macro
to fix it.
So this patch move the calculate and define of MAX_IR_ENTRIES to offline
tool.
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
"S5" is one of the ACPI sleep states which means the function to shut
down the VMs.
On ACRN, the User VM must be shut down before powering off the Service
VM, so we need a vUART channel to communicate between the Service VM
and User VMs.
This patch adds a vUART channel for each User VM connect to Service VM
Tracked-On: #8782
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This patch refine CLOS module by the following aspects:
1 Unified CACHE_ID type to Hex Format
2 Rewrite policy merge with RDT Class
3 Modify the logic of generate CPU mask
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
update the hugepages algorithm as the following steps.
1. calculate the total hugepages of service vm using the formula.
"total memory - the memory consumed by pre-launched VMs - 3G
-1G(memory need by service vm supporting virtio gpu)
-300M*num(number of virtio gpu instance)"
2. calculate hugepage 2M/1G based post-launched vm memory setting.
3. correct the 2M/1G hugepages with the total hugepages in step 1.
"correct_mb, correct_gb= math.modf(total hugepages - the memory
consumed by Post_launched vm)
hugepages_1gb = hugepages_1gb + correct_gb
hugepages_2mb = hugepages_2mb + math.ceil(correct_mb*1024/2)"
Tracked-On: #7301
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
There was an issue of create hv node by clos module, the direct cause
is the create logic and the indirect cause is these modules of
static_allocators was not sorted before run which cause some platform
have issue and CI could not found.
So this patch fix the create issue and sorted the modules list to make
sure all these platform could work well and get the same allocation.xml
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The current RDT setting requires users to calculate the CLOS mask and
the details, it is not a user-friendly setting.
So we redesigned RDT, users can easily specify the cache of each vcpu
for VMs.
This patch add an RDT region element for schema, calculate and generate
all the mask and rdt parameters by config tool to generates rdt_info
struct for board.c.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
1.Unified the function naming style in this file
2.Added the procedure for possible input 0 value of hpa_region in check_hpa()
3.Modified the delimiting spaces between two lines
Tracked-On: #6690
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Ziheng L1 <ziheng.li@intel.com>
According to DX recommendations, this patch adds a Boolean item to each
vCPU which allows users to specify the vCPUs intended for
real-time-critical tasks. This information will be used to organize other
widgets (CAT-related ones for now) in the configurator to tell apart
real-time ones from the others for better clarity.
All vCPUs are by default not real-time-critical, except those in the RT VMs
which are.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The GPA SSRAM area size in pre-launched VMs was hard-coded to 8MB.
Since this area is mapped from host SSRAM area, it will cause compile
problem when host's SSRAM area is larger than 8MB.
To solve this issue, we have to calculate SSRAM area's size in
gpa.py, and generate a macro PRE_RTVM_SW_SRAM_MAX_SIZE for HV
to use.
PRE_RTVM_SW_SRAM_START_GPA/END_GPA can be calculated by end/size
in HV, so they are removed.
When SSRAM is not configured in the system, PRE_RTVM_SW_SRAM_MAX_SIZE
is set to 0.
Crl_bin is not needed in guest. So it's size is removed in bin_gen.py.
Tracked-On: #7212
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
default value of minOccurs is "1", which will trigger problem
when user leave pcpu_id blank while preserve cpu_affinity in
service VM.
Tracked-On: #7267
Signed-off-by: hangliu1 <hang1.liu@linux.intel.com>
Many of the license and Intel copyright headers include the "All rights
reserved" string. It is not relevant in the context of the BSD-3-Clause
license that the code is released under. This patch removes those strings
throughout the code (hypervisor, devicemodel and misc).
Tracked-On: #7254
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
For post-launched RTVM, the acrn-dm can own PMU_PASSTHROUGH flag; for
pre-launched RTVM, need set it in configuration file by default.
Tracked-On: #6966
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
A shared memory region can be provided either by the hypervisor or by the
device model. Before recent schema changes this is telled by the "hv:/" or
"dm:/" prefix.
This patch adds another node under an IVSHMEM region to represent the
provider, following the practice that information in the old-school
encodings is split and put as separate XML nodes.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
As is recommended by UX/DX reviews, the per-VM console virtual UART is now
limited to the following choices:
- Disabled
- a COM port from COM1 to COM4
- PCI based
This patch converts the schema of scenario XMLs to integrate this
recommendation and add logic in the scenario upgrader to migrate data from
old scenario XMLs.
v1 -> v2:
* Update the static allocators and C source transformers according to the
new console vUART config item.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Jiaqing Zhao