config_tools: board_inspector: record all details from RTCT in board XML
Today users still need to manually copy the RTCT binary file when they want to passthrough software SRAM to a pre-launched RTVM, which is far from being user friendly. To get rid of that step, this patch extracts all information from the RTCT table and format them in the board XML which is the only file users need to copy from their target platform to build the hypervisor. The patch that immediately follows will then use such information to generate vRTCT for the pre-launched VM. A side effect of this change is that more ranges, which represents those reported by RTCT such as the CRL binary or the error log area, will be added to the `memory` section of the board XML. The `id` attributes of those range will be used to identify what that range is for. As a result, getting RAM of the physical platform from the board XML requires additional conditions on the `id` attributes to avoid counting non-RAM regions unintendedly. Tracked-On: #7947 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
acrnsi-robot
parent
d7bac88e5e
commit
89d54aa5d1
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@ -67,39 +67,10 @@ def extract_topology(root_node, caches_node):
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return (level, id, type)
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caches_node[:] = sorted(caches_node, key=getkey)
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def extract_tcc_capabilities(caches_node):
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try:
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rtct = parse_rtct()
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if rtct.version == 1:
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for entry in rtct.entries:
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if entry.type == acpiparser.rtct.ACPI_RTCT_V1_TYPE_SoftwareSRAM:
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cache_node = get_node(caches_node, f"cache[@level='{entry.cache_level}' and processors/processor='{hex(entry.apic_id_tbl[0])}']")
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if cache_node is None:
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logging.debug(f"Cannot find the level {entry.cache_level} cache of physical processor with apic ID {entry.apic_id_tbl[0]}")
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continue
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cap = add_child(cache_node, "capability", None, id="Software SRAM")
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add_child(cap, "start", "0x{:08x}".format(entry.base))
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add_child(cap, "end", "0x{:08x}".format(entry.base + entry.size - 1))
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add_child(cap, "size", str(entry.size))
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elif rtct.version == 2:
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for entry in rtct.entries:
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if entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_SoftwareSRAM:
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cache_node = get_node(caches_node, f"cache[@level='{entry.level}' and @id='{hex(entry.cache_id)}']")
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if cache_node is None:
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logging.debug(f"Cannot find the level {entry.level} cache with cache ID {entry.cache_id}")
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continue
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cap = add_child(cache_node, "capability", None, id="Software SRAM")
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add_child(cap, "start", "0x{:08x}".format(entry.base))
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add_child(cap, "end", "0x{:08x}".format(entry.base + entry.size - 1))
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add_child(cap, "size", str(entry.size))
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except FileNotFoundError:
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pass
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def extract(args, board_etree):
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root_node = board_etree.getroot()
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caches_node = get_node(board_etree, "//caches")
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extract_topology(root_node, caches_node)
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extract_tcc_capabilities(caches_node)
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# Inject the explicitly specified CAT capability if exists
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if args.add_llc_cat:
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@ -9,7 +9,7 @@ import re, os, fcntl, errno
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import lxml.etree
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from extractors.helpers import add_child, get_node
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from acpiparser import parse_apic, apic
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import acpiparser
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DEFAULT_MAX_IOAPIC_LINES = 240
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@ -40,16 +40,113 @@ def extract_gsi_number(ioapic_node, apic_id):
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def extract_topology(ioapics_node, tables):
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for subtable in tables.interrupt_controller_structures:
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if subtable.subtype == apic.MADT_TYPE_IO_APIC:
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if subtable.subtype == acpiparser.apic.MADT_TYPE_IO_APIC:
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apic_id = subtable.io_apic_id
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ioapic_node = add_child(ioapics_node, "ioapic", None, id=hex(apic_id))
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add_child(ioapic_node, "address", hex(subtable.io_apic_addr))
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add_child(ioapic_node, "gsi_base", hex(subtable.global_sys_int_base))
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extract_gsi_number(ioapic_node, apic_id)
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def extract_tcc_capabilities_from_rtct_v1(board_etree, rtct):
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caches_node = get_node(board_etree, "//caches")
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for entry in rtct.entries:
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if entry.type == acpiparser.rtct.ACPI_RTCT_V1_TYPE_SoftwareSRAM:
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cache_node = get_node(caches_node, f"cache[@level='{entry.cache_level}' and processors/processor='{hex(entry.apic_id_tbl[0])}']")
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if cache_node is None:
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logging.debug(f"Cannot find the level {entry.cache_level} cache of physical processor with apic ID {entry.apic_id_tbl[0]}")
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continue
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cap = add_child(cache_node, "capability", None, id="Software SRAM")
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add_child(cap, "start", "0x{:08x}".format(entry.base))
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add_child(cap, "end", "0x{:08x}".format(entry.base + entry.size - 1))
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add_child(cap, "size", str(entry.size))
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def extract_tcc_capabilities_from_rtct_v2(board_etree, rtct):
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def get_or_create_ssram_node(cache_node):
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ssram_node = get_node(cache_node, "capability[@id = 'Software SRAM']")
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if ssram_node is None:
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ssram_node = add_child(cache_node, "capability", None, id="Software SRAM")
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return ssram_node
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caches_node = get_node(board_etree, "//caches")
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memory_node = get_node(board_etree, "//memory")
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devices_node = get_node(board_etree, "//devices")
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for entry in rtct.entries:
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cache_node = None
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if hasattr(entry, "level") and hasattr(entry, "cache_id"):
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cache_node = get_node(caches_node, f"cache[@level='{entry.level}' and @id='{hex(entry.cache_id)}']")
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if cache_node is None:
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logging.debug(f"Cannot find the level {entry.level} cache with cache ID {entry.cache_id}")
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continue
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if entry.type == acpiparser.rtct.ACPI_RTCT_TYPE_COMPATIBILITY:
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rtct_version_node = add_child(caches_node, "parameter", None, id="RTCT Version")
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add_child(rtct_version_node, "major", str(entry.rtct_version_major))
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add_child(rtct_version_node, "minor", str(entry.rtct_version_minor))
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rtcd_version_node = add_child(caches_node, "parameter", None, id="RTCD Version")
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add_child(rtcd_version_node, "major", str(entry.rtcd_version_major))
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add_child(rtcd_version_node, "minor", str(entry.rtcd_version_minor))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_RTCD_Limits:
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add_child(caches_node, "parameter", str(entry.total_ia_l2_clos), id="Total IA L2 CLOS")
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add_child(caches_node, "parameter", str(entry.total_ia_l3_clos), id="Total IA L3 CLOS")
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add_child(caches_node, "parameter", str(entry.total_l2_instances), id="Total IA L2 Instances")
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add_child(caches_node, "parameter", str(entry.total_l3_instances), id="Total IA L2 Instances")
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add_child(caches_node, "parameter", str(entry.total_gt_clos), id="Total GT CLOS")
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add_child(caches_node, "parameter", str(entry.total_wrc_clos), id="Total WRC CLOS")
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add_child(devices_node, "parameter", str(entry.max_tcc_streams), id="Maximum TCC Streams")
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add_child(devices_node, "parameter", str(entry.max_tcc_registers), id="Maximum TCC Registers")
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_CRL_Binary:
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start = "0x{:016x}".format(entry.address)
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end = "0x{:016x}".format(entry.address + entry.size - 1)
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size = str(entry.size)
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region = add_child(memory_node, "range", None, id="CRL Binary", start=start, end=end, size=size)
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_IA_WayMasks:
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cap = add_child(cache_node, "parameter", None, id="IA Waymask")
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for waymask in entry.waymask:
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add_child(cap, "waymask", hex(waymask))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_WRC_WayMasks:
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cap = add_child(cache_node, "parameter", None, id="WRC Waymask")
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add_child(cap, "waymask", hex(entry.waymask))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_GT_WayMasks:
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cap = add_child(cache_node, "parameter", None, id="GT Waymask")
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for waymask in entry.waymask:
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add_child(cap, "waymask", hex(waymask))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_SSRAM_WayMask:
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ssram_node = get_or_create_ssram_node(cache_node)
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add_child(ssram_node, "waymask", hex(entry.waymask))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_SoftwareSRAM:
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ssram_node = get_or_create_ssram_node(cache_node)
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add_child(ssram_node, "start", "0x{:08x}".format(entry.base))
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add_child(ssram_node, "end", "0x{:08x}".format(entry.base + entry.size - 1))
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add_child(ssram_node, "size", str(entry.size))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency:
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for cache_id in entry.cache_id:
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cache_node = get_node(caches_node, f"cache[@level='{entry.hierarchy}' and @id='{hex(cache_id)}']")
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if cache_node is None:
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logging.debug(f"Cannot find the level {entry.hierarchy} cache with cache ID {cache_id}")
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continue
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param = add_child(cache_node, "parameter", None, id="Worst Case Access Latency")
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add_child(param, "native", str(entry.clock_cycles))
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elif entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_ErrorLogAddress:
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start = "0x{:016x}".format(entry.address)
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end = "0x{:016x}".format(entry.address + entry.size - 1)
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size = str(entry.size)
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region = add_child(memory_node, "range", None, id="TCC Error Log", start=start, end=end, size=size)
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def extract_tcc_capabilities(board_etree):
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try:
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rtct = acpiparser.parse_rtct()
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if rtct.version == 1:
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extract_tcc_capabilities_from_rtct_v1(board_etree, rtct)
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elif rtct.version == 2:
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extract_tcc_capabilities_from_rtct_v2(board_etree, rtct)
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except FileNotFoundError:
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pass
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def extract(args, board_etree):
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try:
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tables = parse_apic()
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tables = acpiparser.parse_apic()
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except Exception as e:
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logging.warning(f"Parse ACPI tables failed: {str(e)}")
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logging.warning(f"Will not extract information from ACPI tables")
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@ -57,3 +154,5 @@ def extract(args, board_etree):
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ioapics_node = get_node(board_etree, "//ioapics")
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extract_topology(ioapics_node, tables)
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extract_tcc_capabilities(board_etree)
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@ -656,12 +656,3 @@ def generate_info(board_file):
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# Generate board info
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with open(board_file, 'a+') as config:
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gen_acpi_info(config)
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# get the PTCT/RTCT table from native environment
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out_dir = os.path.dirname(board_file)
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if os.path.isfile(SYS_PATH[1] + 'PTCT'):
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shutil.copy(SYS_PATH[1] + 'PTCT', out_dir if out_dir != "" else "./")
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logging.info("PTCT table has been saved to {} successfully!".format(os.path.join(out_dir, 'PTCT')))
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if os.path.isfile(SYS_PATH[1] + 'RTCT'):
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shutil.copy(SYS_PATH[1] + 'RTCT', out_dir if out_dir != "" else "./")
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logging.info("RTCT table has been saved to {} successfully!".format(os.path.join(out_dir, 'RTCT')))
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@ -13,12 +13,10 @@ import common, math, logging
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def import_memory_info(board_etree):
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ram_range = {}
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start = board_etree.xpath("/acrn-config/memory/range/@start")
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size = board_etree.xpath("/acrn-config/memory/range/@size")
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for i in range(len(start)):
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start_hex = int(start[i], 16)
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size_hex = int(size[i], 10)
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ram_range[start_hex] = size_hex
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for memory_range in board_etree.xpath("/acrn-config/memory/range[not(@id) or @id = 'RAM']"):
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start = int(memory_range.get("start"), base=16)
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size = int(memory_range.get("size"), base=10)
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ram_range[start] = size
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return ram_range
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