OrgACRN
/
acrn-hypervisor
mirror of https://github.com/projectacrn/acrn-hypervisor.git
1
0
Fork 0
Code Issues Releases Wiki Activity

hv: Write Buffer Flush - VT-d 

This patch does the following changes
According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers
are flushed implicitly upon Remapping Hardware Caches Invalidation even on
platforms that set RWBF to 1 in capability register. So removed write buffer
flushing as current ACRN issues cache invalidation commands in all cases.

Tracked-On: #1855
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
This commit is contained in:
Sainath Grandhi 2018-12-23 00:17:04 -08:00 committed by wenlingz
parent a5113d922d
commit ef03385f42
2 changed files with 5 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
hypervisor/arch/x86/vtd.c
View File

@ -275,6 +275,11 @@ static void iommu_flush_cache(const struct dmar_drhd_rt *dmar_unit,
} }
#if DBG_IOMMU #if DBG_IOMMU
static inline uint8_t iommu_cap_rwbf(uint64_t cap)
{
return ((uint8_t)(cap >> 4U) & 1U);
}
static void dmar_unit_show_capability(struct dmar_drhd_rt *dmar_unit) static void dmar_unit_show_capability(struct dmar_drhd_rt *dmar_unit)
{ {
pr_info("dmar unit[0x%x]", dmar_unit->drhd->reg_base_addr); pr_info("dmar unit[0x%x]", dmar_unit->drhd->reg_base_addr);
@ -486,20 +491,6 @@ static struct dmar_drhd_rt *device_to_dmaru(uint16_t segment, uint8_t bus, uint8
return dmar_unit; return dmar_unit;
} }
static void dmar_write_buffer_flush(struct dmar_drhd_rt *dmar_unit)
{
uint32_t status;
if (iommu_cap_rwbf(dmar_unit->cap) != 0U) {
spinlock_obtain(&(dmar_unit->lock));
iommu_write32(dmar_unit, DMAR_GCMD_REG, dmar_unit->gcmd | DMA_GCMD_WBF);
/* read lower 32 bits to check */
dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_WBFS, true, &status);
spinlock_release(&(dmar_unit->lock));
}
}
/* /*
* did: domain id * did: domain id
* sid: source id * sid: source id
@ -799,7 +790,6 @@ static void dmar_prepare(struct dmar_drhd_rt *dmar_unit)
static void dmar_enable(struct dmar_drhd_rt *dmar_unit) static void dmar_enable(struct dmar_drhd_rt *dmar_unit)
{ {
dev_dbg(ACRN_DBG_IOMMU, "enable dmar uint [0x%x]", dmar_unit->drhd->reg_base_addr); dev_dbg(ACRN_DBG_IOMMU, "enable dmar uint [0x%x]", dmar_unit->drhd->reg_base_addr);
dmar_write_buffer_flush(dmar_unit);
dmar_invalid_context_cache_global(dmar_unit); dmar_invalid_context_cache_global(dmar_unit);
dmar_invalid_iotlb_global(dmar_unit); dmar_invalid_iotlb_global(dmar_unit);
dmar_enable_translation(dmar_unit); dmar_enable_translation(dmar_unit);
@ -815,8 +805,6 @@ static void dmar_suspend(struct dmar_drhd_rt *dmar_unit)
{ {
uint32_t i; uint32_t i;
/* flush */
dmar_write_buffer_flush(dmar_unit);
dmar_invalid_context_cache_global(dmar_unit); dmar_invalid_context_cache_global(dmar_unit);
dmar_invalid_iotlb_global(dmar_unit); dmar_invalid_iotlb_global(dmar_unit);

5
hypervisor/include/arch/x86/vtd.h
View File

@ -129,11 +129,6 @@ static inline uint8_t iommu_cap_plmr(uint64_t cap)
return ((uint8_t)(cap >> 5U) & 1U); return ((uint8_t)(cap >> 5U) & 1U);
} }
static inline uint8_t iommu_cap_rwbf(uint64_t cap)
{
return ((uint8_t)(cap >> 4U) & 1U);
}
static inline uint8_t iommu_cap_afl(uint64_t cap) static inline uint8_t iommu_cap_afl(uint64_t cap)
{ {
return ((uint8_t)(cap >> 3U) & 1U); return ((uint8_t)(cap >> 3U) & 1U);