From ef03385f424bb2e4416b8bf0d46d3561bb16e40e Mon Sep 17 00:00:00 2001 From: Sainath Grandhi Date: Sun, 23 Dec 2018 00:17:04 -0800 Subject: [PATCH] hv: Write Buffer Flush - VT-d This patch does the following changes According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers are flushed implicitly upon Remapping Hardware Caches Invalidation even on platforms that set RWBF to 1 in capability register. So removed write buffer flushing as current ACRN issues cache invalidation commands in all cases. Tracked-On: #1855 Signed-off-by: Sainath Grandhi --- hypervisor/arch/x86/vtd.c | 22 +++++----------------- hypervisor/include/arch/x86/vtd.h | 5 ----- 2 files changed, 5 insertions(+), 22 deletions(-) diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c index a57b60e29..8b31fc7e8 100644 --- a/hypervisor/arch/x86/vtd.c +++ b/hypervisor/arch/x86/vtd.c @@ -275,6 +275,11 @@ static void iommu_flush_cache(const struct dmar_drhd_rt *dmar_unit, } #if DBG_IOMMU +static inline uint8_t iommu_cap_rwbf(uint64_t cap) +{ + return ((uint8_t)(cap >> 4U) & 1U); +} + static void dmar_unit_show_capability(struct dmar_drhd_rt *dmar_unit) { pr_info("dmar unit[0x%x]", dmar_unit->drhd->reg_base_addr); @@ -486,20 +491,6 @@ static struct dmar_drhd_rt *device_to_dmaru(uint16_t segment, uint8_t bus, uint8 return dmar_unit; } -static void dmar_write_buffer_flush(struct dmar_drhd_rt *dmar_unit) -{ - uint32_t status; - - if (iommu_cap_rwbf(dmar_unit->cap) != 0U) { - spinlock_obtain(&(dmar_unit->lock)); - iommu_write32(dmar_unit, DMAR_GCMD_REG, dmar_unit->gcmd | DMA_GCMD_WBF); - - /* read lower 32 bits to check */ - dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_WBFS, true, &status); - spinlock_release(&(dmar_unit->lock)); - } -} - /* * did: domain id * sid: source id @@ -799,7 +790,6 @@ static void dmar_prepare(struct dmar_drhd_rt *dmar_unit) static void dmar_enable(struct dmar_drhd_rt *dmar_unit) { dev_dbg(ACRN_DBG_IOMMU, "enable dmar uint [0x%x]", dmar_unit->drhd->reg_base_addr); - dmar_write_buffer_flush(dmar_unit); dmar_invalid_context_cache_global(dmar_unit); dmar_invalid_iotlb_global(dmar_unit); dmar_enable_translation(dmar_unit); @@ -815,8 +805,6 @@ static void dmar_suspend(struct dmar_drhd_rt *dmar_unit) { uint32_t i; - /* flush */ - dmar_write_buffer_flush(dmar_unit); dmar_invalid_context_cache_global(dmar_unit); dmar_invalid_iotlb_global(dmar_unit); diff --git a/hypervisor/include/arch/x86/vtd.h b/hypervisor/include/arch/x86/vtd.h index 12787b6c3..22ce67040 100644 --- a/hypervisor/include/arch/x86/vtd.h +++ b/hypervisor/include/arch/x86/vtd.h @@ -129,11 +129,6 @@ static inline uint8_t iommu_cap_plmr(uint64_t cap) return ((uint8_t)(cap >> 5U) & 1U); } -static inline uint8_t iommu_cap_rwbf(uint64_t cap) -{ - return ((uint8_t)(cap >> 4U) & 1U); -} - static inline uint8_t iommu_cap_afl(uint64_t cap) { return ((uint8_t)(cap >> 3U) & 1U);