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hv: pci: add PCIe PM reset check 

Add PCIe PM reset capability check.

Tracked-On: #3465
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1 2019-12-26 23:38:11 +08:00 committed by wenlingz
parent 26670d7ab3
commit e74a9f397d
2 changed files with 10 additions and 0 deletions
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3
hypervisor/hw/pci.c
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@ -481,6 +481,9 @@ static void pci_read_cap(struct pci_pdev *pdev)
for (idx = 0U; idx < len; idx++) { for (idx = 0U; idx < len; idx++) {
pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, (uint32_t)pos + idx, 1U); pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, (uint32_t)pos + idx, 1U);
} }
} else if (cap == PCIY_PMC) {
val = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PMCSR, 4U);
pdev->has_pm_reset = ((val & PCIM_PMCSR_NO_SOFT_RST) == 0U);
} else if (cap == PCIY_PCIE) { } else if (cap == PCIY_PCIE) {
pcie_devcap = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PCIE_DEVCAP, 4U); pcie_devcap = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PCIE_DEVCAP, 4U);
pdev->has_flr = ((pcie_devcap & PCIM_PCIE_FLRCAP) != 0U); pdev->has_flr = ((pcie_devcap & PCIM_PCIE_FLRCAP) != 0U);

7
hypervisor/include/hw/pci.h
View File

@ -131,6 +131,12 @@
#define MSIX_CAPLEN 12U #define MSIX_CAPLEN 12U
#define MSIX_TABLE_ENTRY_SIZE 16U #define MSIX_TABLE_ENTRY_SIZE 16U
/* PCI Power Management Capability */
#define PCIY_PMC 0x01U
/* Power Management Control/Status Register */
#define PCIR_PMCSR 0x04U
#define PCIM_PMCSR_NO_SOFT_RST (0x1U << 3U)
/* PCI Express Capability */ /* PCI Express Capability */
#define PCIY_PCIE 0x10U #define PCIY_PCIE 0x10U
#define PCIR_PCIE_DEVCAP 0x04U #define PCIR_PCIE_DEVCAP 0x04U
@ -195,6 +201,7 @@ struct pci_pdev {
struct pci_msix_cap msix; struct pci_msix_cap msix;
bool has_pm_reset;
bool has_flr; bool has_flr;
bool has_af_flr; bool has_af_flr;
}; };