From e74a9f397dea9b0e62fe15e475e4a804f8c6259b Mon Sep 17 00:00:00 2001 From: Li Fei1 Date: Thu, 26 Dec 2019 23:38:11 +0800 Subject: [PATCH] hv: pci: add PCIe PM reset check Add PCIe PM reset capability check. Tracked-On: #3465 Signed-off-by: Li Fei1 --- hypervisor/hw/pci.c | 3 +++ hypervisor/include/hw/pci.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/hypervisor/hw/pci.c b/hypervisor/hw/pci.c index 6d426f8d1..b5de9a31c 100644 --- a/hypervisor/hw/pci.c +++ b/hypervisor/hw/pci.c @@ -481,6 +481,9 @@ static void pci_read_cap(struct pci_pdev *pdev) for (idx = 0U; idx < len; idx++) { pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, (uint32_t)pos + idx, 1U); } + } else if (cap == PCIY_PMC) { + val = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PMCSR, 4U); + pdev->has_pm_reset = ((val & PCIM_PMCSR_NO_SOFT_RST) == 0U); } else if (cap == PCIY_PCIE) { pcie_devcap = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PCIE_DEVCAP, 4U); pdev->has_flr = ((pcie_devcap & PCIM_PCIE_FLRCAP) != 0U); diff --git a/hypervisor/include/hw/pci.h b/hypervisor/include/hw/pci.h index e370b9ea1..87d9053f8 100644 --- a/hypervisor/include/hw/pci.h +++ b/hypervisor/include/hw/pci.h @@ -131,6 +131,12 @@ #define MSIX_CAPLEN 12U #define MSIX_TABLE_ENTRY_SIZE 16U +/* PCI Power Management Capability */ +#define PCIY_PMC 0x01U +/* Power Management Control/Status Register */ +#define PCIR_PMCSR 0x04U +#define PCIM_PMCSR_NO_SOFT_RST (0x1U << 3U) + /* PCI Express Capability */ #define PCIY_PCIE 0x10U #define PCIR_PCIE_DEVCAP 0x04U @@ -195,6 +201,7 @@ struct pci_pdev { struct pci_msix_cap msix; + bool has_pm_reset; bool has_flr; bool has_af_flr; };