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HV: split L2 and L3 cache resource MSR 

Upcoming intel platforms can support both L2 and L3
but our current code only supports either L2 or L3 CAT.
So split the MSRs so that we can support allocation
for both L2 and L3.

This patch does the following,
1. splits programming of L2 and L3 cache resource
based on the resource ID.
2. Replace generic platform_clos_array struct with resource
specific struct in all the existing board.c files.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj 2020-02-14 16:58:21 -08:00 committed by wenlingz
parent 2597429903
commit b8a021d658
9 changed files with 30 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hypervisor/arch/x86/configs/apl-mrb/board.c
View File

@ -14,7 +14,8 @@
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {

3
hypervisor/arch/x86/configs/apl-up2/board.c
View File

@ -16,7 +16,8 @@
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM] = {
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM] = {
{
.clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_BASE,

3
hypervisor/arch/x86/configs/dnv-cb2/board.c
View File

@ -14,6 +14,7 @@
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

3
hypervisor/arch/x86/configs/generic/board.c
View File

@ -14,6 +14,7 @@
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

3
hypervisor/arch/x86/configs/icl-rvp/board.c
View File

@ -14,6 +14,7 @@
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

3
hypervisor/arch/x86/configs/nuc6cayh/board.c
View File

@ -14,6 +14,7 @@
#endif
struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

3
hypervisor/arch/x86/configs/nuc7i7dnb/board.c
View File

@ -56,6 +56,7 @@ struct dmar_info plat_dmar_info = {
.drhd_units = drhd_info_array,
};
struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

15
hypervisor/arch/x86/rdt.c
View File

@ -67,9 +67,20 @@ void setup_clos(uint16_t pcpu_id)
if (cat_cap_info.enabled) {
for (i = 0U; i < platform_clos_num; i++) {
msr_index = platform_clos_array[i].msr_index;
val = (uint64_t)platform_clos_array[i].clos_mask;
switch (cat_cap_info.res_id) {
case CAT_RESID_L2:
msr_index = platform_l2_clos_array[i].msr_index;
val = (uint64_t)platform_l2_clos_array[i].clos_mask;
msr_write_pcpu(msr_index, val, pcpu_id);
break;
case CAT_RESID_L3:
msr_index = platform_l3_clos_array[i].msr_index;
val = (uint64_t)platform_l3_clos_array[i].clos_mask;
msr_write_pcpu(msr_index, val, pcpu_id);
break;
default:
pr_err("Invalid RDT resource configuration\n");
}
}
/* set hypervisor CAT clos */
msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2prq_msr(hv_clos), pcpu_id);

3
hypervisor/include/arch/x86/board.h
View File

@ -20,7 +20,8 @@ struct platform_clos_info {
};
extern struct dmar_info plat_dmar_info;
extern struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
extern const struct cpu_state_table board_cpu_state_tbl;
extern const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];