From b8a021d658cbb36cfb6a716f59312b2b1028e828 Mon Sep 17 00:00:00 2001 From: Vijay Dhanraj Date: Fri, 14 Feb 2020 16:58:21 -0800 Subject: [PATCH] HV: split L2 and L3 cache resource MSR Upcoming intel platforms can support both L2 and L3 but our current code only supports either L2 or L3 CAT. So split the MSRs so that we can support allocation for both L2 and L3. This patch does the following, 1. splits programming of L2 and L3 cache resource based on the resource ID. 2. Replace generic platform_clos_array struct with resource specific struct in all the existing board.c files. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj Acked-by: Eddie Dong --- hypervisor/arch/x86/configs/apl-mrb/board.c | 3 ++- hypervisor/arch/x86/configs/apl-up2/board.c | 3 ++- hypervisor/arch/x86/configs/dnv-cb2/board.c | 3 ++- hypervisor/arch/x86/configs/generic/board.c | 3 ++- hypervisor/arch/x86/configs/icl-rvp/board.c | 3 ++- hypervisor/arch/x86/configs/nuc6cayh/board.c | 3 ++- hypervisor/arch/x86/configs/nuc7i7dnb/board.c | 3 ++- hypervisor/arch/x86/rdt.c | 17 ++++++++++++++--- hypervisor/include/arch/x86/board.h | 3 ++- 9 files changed, 30 insertions(+), 11 deletions(-) diff --git a/hypervisor/arch/x86/configs/apl-mrb/board.c b/hypervisor/arch/x86/configs/apl-mrb/board.c index b7fc70e58..39a4fe849 100644 --- a/hypervisor/arch/x86/configs/apl-mrb/board.c +++ b/hypervisor/arch/x86/configs/apl-mrb/board.c @@ -14,7 +14,8 @@ #endif struct dmar_info plat_dmar_info; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; const struct cpu_state_table board_cpu_state_tbl; const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = { diff --git a/hypervisor/arch/x86/configs/apl-up2/board.c b/hypervisor/arch/x86/configs/apl-up2/board.c index bdd974839..88789767f 100644 --- a/hypervisor/arch/x86/configs/apl-up2/board.c +++ b/hypervisor/arch/x86/configs/apl-up2/board.c @@ -16,7 +16,8 @@ struct dmar_info plat_dmar_info; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM] = { +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM] = { { .clos_mask = 0xff, .msr_index = MSR_IA32_L2_MASK_BASE, diff --git a/hypervisor/arch/x86/configs/dnv-cb2/board.c b/hypervisor/arch/x86/configs/dnv-cb2/board.c index fed30e6fc..b87453bc2 100644 --- a/hypervisor/arch/x86/configs/dnv-cb2/board.c +++ b/hypervisor/arch/x86/configs/dnv-cb2/board.c @@ -14,6 +14,7 @@ #endif struct dmar_info plat_dmar_info; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; const struct cpu_state_table board_cpu_state_tbl; const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; diff --git a/hypervisor/arch/x86/configs/generic/board.c b/hypervisor/arch/x86/configs/generic/board.c index fed30e6fc..b87453bc2 100644 --- a/hypervisor/arch/x86/configs/generic/board.c +++ b/hypervisor/arch/x86/configs/generic/board.c @@ -14,6 +14,7 @@ #endif struct dmar_info plat_dmar_info; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; const struct cpu_state_table board_cpu_state_tbl; const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; diff --git a/hypervisor/arch/x86/configs/icl-rvp/board.c b/hypervisor/arch/x86/configs/icl-rvp/board.c index fed30e6fc..b87453bc2 100644 --- a/hypervisor/arch/x86/configs/icl-rvp/board.c +++ b/hypervisor/arch/x86/configs/icl-rvp/board.c @@ -14,6 +14,7 @@ #endif struct dmar_info plat_dmar_info; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; const struct cpu_state_table board_cpu_state_tbl; const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; diff --git a/hypervisor/arch/x86/configs/nuc6cayh/board.c b/hypervisor/arch/x86/configs/nuc6cayh/board.c index fed30e6fc..b87453bc2 100644 --- a/hypervisor/arch/x86/configs/nuc6cayh/board.c +++ b/hypervisor/arch/x86/configs/nuc6cayh/board.c @@ -14,6 +14,7 @@ #endif struct dmar_info plat_dmar_info; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; const struct cpu_state_table board_cpu_state_tbl; const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; diff --git a/hypervisor/arch/x86/configs/nuc7i7dnb/board.c b/hypervisor/arch/x86/configs/nuc7i7dnb/board.c index 096fb883c..612635195 100644 --- a/hypervisor/arch/x86/configs/nuc7i7dnb/board.c +++ b/hypervisor/arch/x86/configs/nuc7i7dnb/board.c @@ -56,6 +56,7 @@ struct dmar_info plat_dmar_info = { .drhd_units = drhd_info_array, }; -struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; const struct cpu_state_table board_cpu_state_tbl; const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; diff --git a/hypervisor/arch/x86/rdt.c b/hypervisor/arch/x86/rdt.c index adb208dc2..b76838ad0 100644 --- a/hypervisor/arch/x86/rdt.c +++ b/hypervisor/arch/x86/rdt.c @@ -67,9 +67,20 @@ void setup_clos(uint16_t pcpu_id) if (cat_cap_info.enabled) { for (i = 0U; i < platform_clos_num; i++) { - msr_index = platform_clos_array[i].msr_index; - val = (uint64_t)platform_clos_array[i].clos_mask; - msr_write_pcpu(msr_index, val, pcpu_id); + switch (cat_cap_info.res_id) { + case CAT_RESID_L2: + msr_index = platform_l2_clos_array[i].msr_index; + val = (uint64_t)platform_l2_clos_array[i].clos_mask; + msr_write_pcpu(msr_index, val, pcpu_id); + break; + case CAT_RESID_L3: + msr_index = platform_l3_clos_array[i].msr_index; + val = (uint64_t)platform_l3_clos_array[i].clos_mask; + msr_write_pcpu(msr_index, val, pcpu_id); + break; + default: + pr_err("Invalid RDT resource configuration\n"); + } } /* set hypervisor CAT clos */ msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2prq_msr(hv_clos), pcpu_id); diff --git a/hypervisor/include/arch/x86/board.h b/hypervisor/include/arch/x86/board.h index b10a0ff0e..aea17e9ad 100644 --- a/hypervisor/include/arch/x86/board.h +++ b/hypervisor/include/arch/x86/board.h @@ -20,7 +20,8 @@ struct platform_clos_info { }; extern struct dmar_info plat_dmar_info; -extern struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM]; +extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; extern const struct cpu_state_table board_cpu_state_tbl; extern const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];