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hv: add missing MSRs to unsupported_msrs[] 

SMRR (System-Management Range Register) is disabled from vMTRR,
so treat IA32_SMRR_PHYSBASE and IA32_SMRR_PHYSMASK as unsupported.

IA32_SMBASE is available only when IA32_VMX_MISC[15] is set.

IA32_FIXED_CTR0/1/2 are available only when CPUID.0AH:EDX[4:0] is non-zero.

Intel Processor Trace feature has been disabled and the associated MSRs
need to be in unsupported_msr[] as well.

Tracked-On: #1867
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen 2019-01-03 11:44:40 -08:00 committed by wenlingz
parent 97cb7d906e
commit a4b166d5e8
2 changed files with 26 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
hypervisor/arch/x86/guest/vmsr.c
View File

@ -53,7 +53,7 @@ static const uint32_t mtrr_msrs[NUM_MTRR_MSRS] = {
};
/* Following MSRs are intercepted, but it throws GPs for any guest accesses */
#define NUM_UNSUPPORTED_MSRS 76U
#define NUM_UNSUPPORTED_MSRS 95U
static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
/* Variable MTRRs are not supported */
MSR_IA32_MTRR_PHYSBASE_0,
@ -76,8 +76,11 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
MSR_IA32_MTRR_PHYSMASK_8,
MSR_IA32_MTRR_PHYSBASE_9,
MSR_IA32_MTRR_PHYSMASK_9,
MSR_IA32_SMRR_PHYSBASE,
MSR_IA32_SMRR_PHYSMASK,
/* No level 2 VMX: CPUID.01H.ECX[5] */
MSR_IA32_SMBASE,
MSR_IA32_VMX_BASIC,
MSR_IA32_VMX_PINBASED_CTLS,
MSR_IA32_VMX_PROCBASED_CTLS,
@ -138,6 +141,10 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
MSR_IA32_PERF_GLOBAL_OVF_CTRL,
MSR_IA32_PERF_GLOBAL_STATUS_SET,
MSR_IA32_PERF_GLOBAL_INUSE,
/* CPUID.0AH.EDX[4:0] */
MSR_IA32_FIXED_CTR0,
MSR_IA32_FIXED_CTR1,
MSR_IA32_FIXED_CTR2,
/* QOS Configuration disabled: CPUID.10H.ECX[2] */
MSR_IA32_L3_QOS_CFG,
@ -146,10 +153,26 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
/* RDT-M disabled: CPUID.07H.EBX[12], CPUID.07H.EBX[15] */
MSR_IA32_QM_EVTSEL,
MSR_IA32_QM_CTR,
MSR_IA32_PQR_ASSOC
MSR_IA32_PQR_ASSOC,
/* RDT-A disabled: CPUID.07H.EBX[12], CPUID.10H */
/* MSR 0xC90 ... 0xD8F, not in this array */
/* RTIT disabled: CPUID.07H.EBX[25], CPUID.14H.ECX[0,2] (X86_FEATURE_INTEL_PT) */
MSR_IA32_RTIT_OUTPUT_BASE,
MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
MSR_IA32_RTIT_CTL,
MSR_IA32_RTIT_STATUS,
MSR_IA32_RTIT_CR3_MATCH,
/* Region Address: CPUID.07H.EAX[2:0] (subleaf 1) */
MSR_IA32_RTIT_ADDR0_A,
MSR_IA32_RTIT_ADDR0_B,
MSR_IA32_RTIT_ADDR1_A,
MSR_IA32_RTIT_ADDR1_B,
MSR_IA32_RTIT_ADDR2_A,
MSR_IA32_RTIT_ADDR2_B,
MSR_IA32_RTIT_ADDR3_A,
MSR_IA32_RTIT_ADDR3_B,
};
#define NUM_X2APIC_MSRS 44U

1
hypervisor/include/arch/x86/msr.h
View File

@ -31,6 +31,7 @@
#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008EU
#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008FU
#define MSR_IA32_SMM_MONITOR_CTL 0x0000009BU
#define MSR_IA32_SMBASE 0x0000009EU
#define MSR_IA32_PMC0 0x000000C1U
#define MSR_IA32_PMC1 0x000000C2U
#define MSR_IA32_PMC2 0x000000C3U