diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index 1b7672c7e..dd4064a89 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -53,7 +53,7 @@ static const uint32_t mtrr_msrs[NUM_MTRR_MSRS] = {
 };
 
 /* Following MSRs are intercepted, but it throws GPs for any guest accesses */
-#define NUM_UNSUPPORTED_MSRS	76U
+#define NUM_UNSUPPORTED_MSRS	95U
 static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
 	/* Variable MTRRs are not supported */
 	MSR_IA32_MTRR_PHYSBASE_0,
@@ -76,8 +76,11 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
 	MSR_IA32_MTRR_PHYSMASK_8,
 	MSR_IA32_MTRR_PHYSBASE_9,
 	MSR_IA32_MTRR_PHYSMASK_9,
+	MSR_IA32_SMRR_PHYSBASE,
+	MSR_IA32_SMRR_PHYSMASK,
 
 	/* No level 2 VMX: CPUID.01H.ECX[5] */
+	MSR_IA32_SMBASE,
 	MSR_IA32_VMX_BASIC,
 	MSR_IA32_VMX_PINBASED_CTLS,
 	MSR_IA32_VMX_PROCBASED_CTLS,
@@ -138,6 +141,10 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
 	MSR_IA32_PERF_GLOBAL_OVF_CTRL,
 	MSR_IA32_PERF_GLOBAL_STATUS_SET,
 	MSR_IA32_PERF_GLOBAL_INUSE,
+	/* CPUID.0AH.EDX[4:0] */
+	MSR_IA32_FIXED_CTR0,
+	MSR_IA32_FIXED_CTR1,
+	MSR_IA32_FIXED_CTR2,
 
 	/* QOS Configuration disabled: CPUID.10H.ECX[2] */
 	MSR_IA32_L3_QOS_CFG,
@@ -146,10 +153,26 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
 	/* RDT-M disabled: CPUID.07H.EBX[12], CPUID.07H.EBX[15] */
 	MSR_IA32_QM_EVTSEL,
 	MSR_IA32_QM_CTR,
-	MSR_IA32_PQR_ASSOC
+	MSR_IA32_PQR_ASSOC,
 
 	/* RDT-A disabled: CPUID.07H.EBX[12], CPUID.10H */
 	/* MSR 0xC90 ... 0xD8F, not in this array */
+
+	/* RTIT disabled: CPUID.07H.EBX[25], CPUID.14H.ECX[0,2] (X86_FEATURE_INTEL_PT) */
+	MSR_IA32_RTIT_OUTPUT_BASE,
+	MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
+	MSR_IA32_RTIT_CTL,
+	MSR_IA32_RTIT_STATUS,
+	MSR_IA32_RTIT_CR3_MATCH,
+	/* Region Address: CPUID.07H.EAX[2:0] (subleaf 1) */
+	MSR_IA32_RTIT_ADDR0_A,
+	MSR_IA32_RTIT_ADDR0_B,
+	MSR_IA32_RTIT_ADDR1_A,
+	MSR_IA32_RTIT_ADDR1_B,
+	MSR_IA32_RTIT_ADDR2_A,
+	MSR_IA32_RTIT_ADDR2_B,
+	MSR_IA32_RTIT_ADDR3_A,
+	MSR_IA32_RTIT_ADDR3_B,
 };
 
 #define NUM_X2APIC_MSRS	44U
diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h
index 61484ce63..0fbbfcb56 100644
--- a/hypervisor/include/arch/x86/msr.h
+++ b/hypervisor/include/arch/x86/msr.h
@@ -31,6 +31,7 @@
 #define MSR_IA32_SGXLEPUBKEYHASH2		0x0000008EU
 #define MSR_IA32_SGXLEPUBKEYHASH3		0x0000008FU
 #define MSR_IA32_SMM_MONITOR_CTL		0x0000009BU
+#define MSR_IA32_SMBASE				0x0000009EU
 #define MSR_IA32_PMC0				0x000000C1U
 #define MSR_IA32_PMC1				0x000000C2U
 #define MSR_IA32_PMC2				0x000000C3U