HV:interrupt:fix "signed/unsigned conversion without cast"
Misra C required signed/unsigned conversion with cast. V1->V2: a.split patch to patch series V2->V3: a.change the uint64_t type numeric constant's suffix from U to UL Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
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102d2f1a68
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95736e659f
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@ -114,19 +114,19 @@ ioapic_write_reg32(const void *ioapic_base,
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}
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}
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static inline uint64_t
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static inline uint64_t
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get_ioapic_base(int apic_id)
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get_ioapic_base(uint8_t apic_id)
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{
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{
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uint64_t addr = -1UL;
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uint64_t addr = 0xffffffffffffffffUL;
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/* should extract next ioapic from ACPI MADT table */
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/* should extract next ioapic from ACPI MADT table */
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if (apic_id == 0)
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if (apic_id == 0U)
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addr = DEFAULT_IO_APIC_BASE;
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addr = DEFAULT_IO_APIC_BASE;
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else if (apic_id == 1)
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else if (apic_id == 1U)
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addr = 0xfec3f000;
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addr = 0xfec3f000UL;
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else if (apic_id == 2)
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else if (apic_id == 2U)
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addr = 0xfec7f000;
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addr = 0xfec7f000UL;
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else
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else
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ASSERT(apic_id <= 2, "ACPI MADT table missing");
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ASSERT(apic_id <= 2U, "ACPI MADT table missing");
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return addr;
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return addr;
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}
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}
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@ -273,7 +273,7 @@ uint32_t pin_to_irq(int pin)
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if (pin < 0)
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if (pin < 0)
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return IRQ_INVALID;
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return IRQ_INVALID;
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for (i = 0; i < nr_gsi; i++) {
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for (i = 0U; i < nr_gsi; i++) {
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if (gsi_table[i].pin == (uint8_t) pin)
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if (gsi_table[i].pin == (uint8_t) pin)
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return i;
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return i;
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}
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}
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@ -302,13 +302,14 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask)
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void setup_ioapic_irq(void)
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void setup_ioapic_irq(void)
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{
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{
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int ioapic_id;
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uint8_t ioapic_id;
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uint32_t gsi;
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uint32_t gsi = 0U;
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uint32_t vr;
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uint32_t vr;
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spinlock_init(&ioapic_lock);
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spinlock_init(&ioapic_lock);
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for (ioapic_id = 0, gsi = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
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for (ioapic_id = 0U;
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ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
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int pin;
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int pin;
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int max_pins;
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int max_pins;
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int version;
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int version;
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@ -349,7 +350,7 @@ void setup_ioapic_irq(void)
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continue;
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continue;
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}
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}
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} else
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} else
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vr = 0; /* not to allocate VR right now */
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vr = 0U; /* not to allocate VR right now */
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ioapic_set_routing(gsi, vr);
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ioapic_set_routing(gsi, vr);
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gsi++;
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gsi++;
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@ -365,7 +366,7 @@ void dump_ioapic(void)
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{
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{
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uint32_t irq;
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uint32_t irq;
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for (irq = 0; irq < nr_gsi; irq++) {
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for (irq = 0U; irq < nr_gsi; irq++) {
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void *addr = gsi_table[irq].addr;
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void *addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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struct ioapic_rte rte;
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@ -429,14 +430,15 @@ void get_rte_info(struct ioapic_rte *rte, bool *mask, bool *irr,
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int get_ioapic_info(char *str, int str_max_len)
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int get_ioapic_info(char *str, int str_max_len)
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{
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{
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uint32_t irq, len, size = str_max_len;
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uint32_t irq;
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int len, size = str_max_len;
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len = snprintf(str, size,
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len = snprintf(str, size,
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"\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK");
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"\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK");
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size -= len;
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size -= len;
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str += len;
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str += len;
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for (irq = 0; irq < nr_gsi; irq++) {
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for (irq = 0U; irq < nr_gsi; irq++) {
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void *addr = gsi_table[irq].addr;
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void *addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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struct ioapic_rte rte;
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@ -6,7 +6,7 @@
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#include <hypervisor.h>
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#include <hypervisor.h>
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static spinlock_t exception_spinlock = { .head = 0, .tail = 0, };
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static spinlock_t exception_spinlock = { .head = 0U, .tail = 0U, };
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static struct irq_desc *irq_desc_base;
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static struct irq_desc *irq_desc_base;
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static uint32_t vector_to_irq[NR_MAX_VECTOR + 1];
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static uint32_t vector_to_irq[NR_MAX_VECTOR + 1];
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@ -25,13 +25,13 @@ static void init_irq_desc(void)
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ASSERT(irq_desc_base != NULL, "page alloc failed!");
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ASSERT(irq_desc_base != NULL, "page alloc failed!");
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memset(irq_desc_base, 0, page_num * CPU_PAGE_SIZE);
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memset(irq_desc_base, 0, page_num * CPU_PAGE_SIZE);
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for (i = 0; i < NR_MAX_IRQS; i++) {
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for (i = 0U; i < NR_MAX_IRQS; i++) {
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irq_desc_base[i].irq = i;
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irq_desc_base[i].irq = i;
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irq_desc_base[i].vector = VECTOR_INVALID;
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irq_desc_base[i].vector = VECTOR_INVALID;
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spinlock_init(&irq_desc_base[i].irq_lock);
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spinlock_init(&irq_desc_base[i].irq_lock);
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}
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}
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for (i = 0; i <= NR_MAX_VECTOR; i++)
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for (i = 0U; i <= NR_MAX_VECTOR; i++)
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vector_to_irq[i] = IRQ_INVALID;
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vector_to_irq[i] = IRQ_INVALID;
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}
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}
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@ -135,7 +135,7 @@ static void _irq_desc_free_vector(uint32_t irq)
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{
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{
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struct irq_desc *desc;
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struct irq_desc *desc;
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uint32_t vr;
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uint32_t vr;
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int pcpu_id;
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uint16_t pcpu_id;
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if (irq > NR_MAX_IRQS)
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if (irq > NR_MAX_IRQS)
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return;
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return;
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@ -151,8 +151,8 @@ static void _irq_desc_free_vector(uint32_t irq)
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if (vector_to_irq[vr] == irq)
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if (vector_to_irq[vr] == irq)
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vector_to_irq[vr] = IRQ_INVALID;
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vector_to_irq[vr] = IRQ_INVALID;
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for (pcpu_id = 0; pcpu_id < phys_cpu_num; pcpu_id++)
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for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++)
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per_cpu(irq_count, pcpu_id)[irq] = 0;
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per_cpu(irq_count, pcpu_id)[irq] = 0UL;
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}
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}
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static void disable_pic_irq(void)
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static void disable_pic_irq(void)
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@ -361,7 +361,7 @@ uint32_t dev_to_vector(struct dev_handler_node *node)
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int init_default_irqs(uint16_t cpu_id)
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int init_default_irqs(uint16_t cpu_id)
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{
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{
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if (cpu_id > 0)
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if (cpu_id != CPU_BOOT_ID)
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return 0;
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return 0;
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init_irq_desc();
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init_irq_desc();
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@ -668,13 +668,14 @@ pri_register_handler(uint32_t irq,
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void get_cpu_interrupt_info(char *str, int str_max)
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void get_cpu_interrupt_info(char *str, int str_max)
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{
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{
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uint16_t pcpu_id;
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uint16_t pcpu_id;
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uint32_t irq, vector, len, size = str_max;
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uint32_t irq, vector;
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int len, size = str_max;
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struct irq_desc *desc;
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struct irq_desc *desc;
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len = snprintf(str, size, "\r\nIRQ\tVECTOR");
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len = snprintf(str, size, "\r\nIRQ\tVECTOR");
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size -= len;
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size -= len;
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str += len;
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str += len;
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for (pcpu_id = 0; pcpu_id < phys_cpu_num; pcpu_id++) {
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for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) {
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len = snprintf(str, size, "\tCPU%d", pcpu_id);
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len = snprintf(str, size, "\tCPU%d", pcpu_id);
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size -= len;
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size -= len;
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str += len;
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str += len;
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@ -683,7 +684,7 @@ void get_cpu_interrupt_info(char *str, int str_max)
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size -= len;
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size -= len;
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str += len;
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str += len;
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for (irq = 0; irq < NR_MAX_IRQS; irq++) {
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for (irq = 0U; irq < NR_MAX_IRQS; irq++) {
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desc = irq_desc_base + irq;
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desc = irq_desc_base + irq;
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vector = irq_to_vector(irq);
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vector = irq_to_vector(irq);
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if (desc->used != IRQ_NOT_ASSIGNED &&
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if (desc->used != IRQ_NOT_ASSIGNED &&
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@ -691,7 +692,7 @@ void get_cpu_interrupt_info(char *str, int str_max)
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len = snprintf(str, size, "\r\n%d\t0x%X", irq, vector);
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len = snprintf(str, size, "\r\n%d\t0x%X", irq, vector);
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size -= len;
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size -= len;
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str += len;
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str += len;
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for (pcpu_id = 0; pcpu_id < phys_cpu_num; pcpu_id++) {
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for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) {
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len = snprintf(str, size, "\t%d",
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len = snprintf(str, size, "\t%d",
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per_cpu(irq_count, pcpu_id)[irq]);
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per_cpu(irq_count, pcpu_id)[irq]);
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size -= len;
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size -= len;
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@ -10,7 +10,7 @@
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#define APIC_TIMER_MAX 0xffffffff
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#define APIC_TIMER_MAX 0xffffffff
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#define HYPE_PERIOD_MAX 1000
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#define HYPE_PERIOD_MAX 1000
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#define APIC_DIVIDE_BY_ONE 0x0b
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#define APIC_DIVIDE_BY_ONE 0x0b
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#define PIT_TARGET 0x3FFF
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#define PIT_TARGET 0x3FFFU
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/* xAPIC/x2APIC Interrupt Command Register (ICR) structure */
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/* xAPIC/x2APIC Interrupt Command Register (ICR) structure */
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union apic_icr {
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union apic_icr {
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@ -221,7 +221,7 @@ void check_tsc(void)
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static uint64_t pit_calibrate_tsc(uint16_t cal_ms)
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static uint64_t pit_calibrate_tsc(uint16_t cal_ms)
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{
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{
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#define PIT_TICK_RATE 1193182UL
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#define PIT_TICK_RATE 1193182UL
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#define PIT_TARGET 0x3FFF
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#define PIT_TARGET 0x3FFFU
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#define PIT_MAX_COUNT 0xFFFF
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#define PIT_MAX_COUNT 0xFFFF
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uint16_t initial_pit;
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uint16_t initial_pit;
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@ -229,13 +229,13 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms)
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uint16_t max_cal_ms;
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uint16_t max_cal_ms;
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uint64_t current_tsc;
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uint64_t current_tsc;
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max_cal_ms = (PIT_MAX_COUNT - PIT_TARGET) * 1000 / PIT_TICK_RATE;
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max_cal_ms = (PIT_MAX_COUNT - PIT_TARGET) * 1000U / PIT_TICK_RATE;
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cal_ms = min(cal_ms, max_cal_ms);
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cal_ms = min(cal_ms, max_cal_ms);
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/* Assume the 8254 delivers 18.2 ticks per second when 16 bits fully
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/* Assume the 8254 delivers 18.2 ticks per second when 16 bits fully
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* wrap. This is about 1.193MHz or a clock period of 0.8384uSec
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* wrap. This is about 1.193MHz or a clock period of 0.8384uSec
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*/
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*/
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initial_pit = (uint16_t)(cal_ms * PIT_TICK_RATE / 1000);
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initial_pit = (uint16_t)(cal_ms * PIT_TICK_RATE / 1000U);
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initial_pit += PIT_TARGET;
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initial_pit += PIT_TARGET;
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/* Port 0x43 ==> Control word write; Data 0x30 ==> Select Counter 0,
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/* Port 0x43 ==> Control word write; Data 0x30 ==> Select Counter 0,
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@ -261,7 +261,7 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms)
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current_tsc = rdtsc() - current_tsc;
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current_tsc = rdtsc() - current_tsc;
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return current_tsc / cal_ms * 1000;
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return current_tsc / cal_ms * 1000U;
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}
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}
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/*
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/*
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@ -437,7 +437,7 @@ struct ioapic {
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*/
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*/
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/* default physical locations of an IO APIC */
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/* default physical locations of an IO APIC */
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#define DEFAULT_IO_APIC_BASE 0xfec00000U
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#define DEFAULT_IO_APIC_BASE 0xfec00000UL
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/* window register offset */
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/* window register offset */
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#define IOAPIC_WINDOW 0x10U
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#define IOAPIC_WINDOW 0x10U
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@ -11,7 +11,7 @@
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* The usable RTEs may be a subset of the total on a per IO APIC basis.
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* The usable RTEs may be a subset of the total on a per IO APIC basis.
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*/
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*/
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#define IOAPIC_MAX_LINES 120
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#define IOAPIC_MAX_LINES 120
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#define NR_LEGACY_IRQ 16
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#define NR_LEGACY_IRQ 16U
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#define NR_LEGACY_PIN NR_LEGACY_IRQ
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#define NR_LEGACY_PIN NR_LEGACY_IRQ
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#define NR_MAX_GSI (CONFIG_NR_IOAPICS*IOAPIC_MAX_LINES)
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#define NR_MAX_GSI (CONFIG_NR_IOAPICS*IOAPIC_MAX_LINES)
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