From 95736e659fac01217f500e9f98bce4291cb1b301 Mon Sep 17 00:00:00 2001 From: Huihuang Shi Date: Tue, 3 Jul 2018 11:52:30 +0800 Subject: [PATCH] HV:interrupt:fix "signed/unsigned conversion without cast" Misra C required signed/unsigned conversion with cast. V1->V2: a.split patch to patch series V2->V3: a.change the uint64_t type numeric constant's suffix from U to UL Signed-off-by: Huihuang Shi Acked-by: Eddie Dong --- hypervisor/arch/x86/ioapic.c | 34 ++++++++++++++------------- hypervisor/arch/x86/irq.c | 23 +++++++++--------- hypervisor/arch/x86/lapic.c | 2 +- hypervisor/arch/x86/timer.c | 8 +++---- hypervisor/include/arch/x86/apicreg.h | 2 +- hypervisor/include/arch/x86/ioapic.h | 2 +- 6 files changed, 37 insertions(+), 34 deletions(-) diff --git a/hypervisor/arch/x86/ioapic.c b/hypervisor/arch/x86/ioapic.c index 7582d2ebc..7361d7038 100644 --- a/hypervisor/arch/x86/ioapic.c +++ b/hypervisor/arch/x86/ioapic.c @@ -114,19 +114,19 @@ ioapic_write_reg32(const void *ioapic_base, } static inline uint64_t -get_ioapic_base(int apic_id) +get_ioapic_base(uint8_t apic_id) { - uint64_t addr = -1UL; + uint64_t addr = 0xffffffffffffffffUL; /* should extract next ioapic from ACPI MADT table */ - if (apic_id == 0) + if (apic_id == 0U) addr = DEFAULT_IO_APIC_BASE; - else if (apic_id == 1) - addr = 0xfec3f000; - else if (apic_id == 2) - addr = 0xfec7f000; + else if (apic_id == 1U) + addr = 0xfec3f000UL; + else if (apic_id == 2U) + addr = 0xfec7f000UL; else - ASSERT(apic_id <= 2, "ACPI MADT table missing"); + ASSERT(apic_id <= 2U, "ACPI MADT table missing"); return addr; } @@ -273,7 +273,7 @@ uint32_t pin_to_irq(int pin) if (pin < 0) return IRQ_INVALID; - for (i = 0; i < nr_gsi; i++) { + for (i = 0U; i < nr_gsi; i++) { if (gsi_table[i].pin == (uint8_t) pin) return i; } @@ -302,13 +302,14 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask) void setup_ioapic_irq(void) { - int ioapic_id; - uint32_t gsi; + uint8_t ioapic_id; + uint32_t gsi = 0U; uint32_t vr; spinlock_init(&ioapic_lock); - for (ioapic_id = 0, gsi = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) { + for (ioapic_id = 0U; + ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) { int pin; int max_pins; int version; @@ -349,7 +350,7 @@ void setup_ioapic_irq(void) continue; } } else - vr = 0; /* not to allocate VR right now */ + vr = 0U; /* not to allocate VR right now */ ioapic_set_routing(gsi, vr); gsi++; @@ -365,7 +366,7 @@ void dump_ioapic(void) { uint32_t irq; - for (irq = 0; irq < nr_gsi; irq++) { + for (irq = 0U; irq < nr_gsi; irq++) { void *addr = gsi_table[irq].addr; int pin = gsi_table[irq].pin; struct ioapic_rte rte; @@ -429,14 +430,15 @@ void get_rte_info(struct ioapic_rte *rte, bool *mask, bool *irr, int get_ioapic_info(char *str, int str_max_len) { - uint32_t irq, len, size = str_max_len; + uint32_t irq; + int len, size = str_max_len; len = snprintf(str, size, "\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK"); size -= len; str += len; - for (irq = 0; irq < nr_gsi; irq++) { + for (irq = 0U; irq < nr_gsi; irq++) { void *addr = gsi_table[irq].addr; int pin = gsi_table[irq].pin; struct ioapic_rte rte; diff --git a/hypervisor/arch/x86/irq.c b/hypervisor/arch/x86/irq.c index e9db33f12..fdea0a7da 100644 --- a/hypervisor/arch/x86/irq.c +++ b/hypervisor/arch/x86/irq.c @@ -6,7 +6,7 @@ #include -static spinlock_t exception_spinlock = { .head = 0, .tail = 0, }; +static spinlock_t exception_spinlock = { .head = 0U, .tail = 0U, }; static struct irq_desc *irq_desc_base; static uint32_t vector_to_irq[NR_MAX_VECTOR + 1]; @@ -25,13 +25,13 @@ static void init_irq_desc(void) ASSERT(irq_desc_base != NULL, "page alloc failed!"); memset(irq_desc_base, 0, page_num * CPU_PAGE_SIZE); - for (i = 0; i < NR_MAX_IRQS; i++) { + for (i = 0U; i < NR_MAX_IRQS; i++) { irq_desc_base[i].irq = i; irq_desc_base[i].vector = VECTOR_INVALID; spinlock_init(&irq_desc_base[i].irq_lock); } - for (i = 0; i <= NR_MAX_VECTOR; i++) + for (i = 0U; i <= NR_MAX_VECTOR; i++) vector_to_irq[i] = IRQ_INVALID; } @@ -135,7 +135,7 @@ static void _irq_desc_free_vector(uint32_t irq) { struct irq_desc *desc; uint32_t vr; - int pcpu_id; + uint16_t pcpu_id; if (irq > NR_MAX_IRQS) return; @@ -151,8 +151,8 @@ static void _irq_desc_free_vector(uint32_t irq) if (vector_to_irq[vr] == irq) vector_to_irq[vr] = IRQ_INVALID; - for (pcpu_id = 0; pcpu_id < phys_cpu_num; pcpu_id++) - per_cpu(irq_count, pcpu_id)[irq] = 0; + for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) + per_cpu(irq_count, pcpu_id)[irq] = 0UL; } static void disable_pic_irq(void) @@ -361,7 +361,7 @@ uint32_t dev_to_vector(struct dev_handler_node *node) int init_default_irqs(uint16_t cpu_id) { - if (cpu_id > 0) + if (cpu_id != CPU_BOOT_ID) return 0; init_irq_desc(); @@ -668,13 +668,14 @@ pri_register_handler(uint32_t irq, void get_cpu_interrupt_info(char *str, int str_max) { uint16_t pcpu_id; - uint32_t irq, vector, len, size = str_max; + uint32_t irq, vector; + int len, size = str_max; struct irq_desc *desc; len = snprintf(str, size, "\r\nIRQ\tVECTOR"); size -= len; str += len; - for (pcpu_id = 0; pcpu_id < phys_cpu_num; pcpu_id++) { + for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) { len = snprintf(str, size, "\tCPU%d", pcpu_id); size -= len; str += len; @@ -683,7 +684,7 @@ void get_cpu_interrupt_info(char *str, int str_max) size -= len; str += len; - for (irq = 0; irq < NR_MAX_IRQS; irq++) { + for (irq = 0U; irq < NR_MAX_IRQS; irq++) { desc = irq_desc_base + irq; vector = irq_to_vector(irq); if (desc->used != IRQ_NOT_ASSIGNED && @@ -691,7 +692,7 @@ void get_cpu_interrupt_info(char *str, int str_max) len = snprintf(str, size, "\r\n%d\t0x%X", irq, vector); size -= len; str += len; - for (pcpu_id = 0; pcpu_id < phys_cpu_num; pcpu_id++) { + for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) { len = snprintf(str, size, "\t%d", per_cpu(irq_count, pcpu_id)[irq]); size -= len; diff --git a/hypervisor/arch/x86/lapic.c b/hypervisor/arch/x86/lapic.c index 8446c0ef6..17ac99f80 100644 --- a/hypervisor/arch/x86/lapic.c +++ b/hypervisor/arch/x86/lapic.c @@ -10,7 +10,7 @@ #define APIC_TIMER_MAX 0xffffffff #define HYPE_PERIOD_MAX 1000 #define APIC_DIVIDE_BY_ONE 0x0b -#define PIT_TARGET 0x3FFF +#define PIT_TARGET 0x3FFFU /* xAPIC/x2APIC Interrupt Command Register (ICR) structure */ union apic_icr { diff --git a/hypervisor/arch/x86/timer.c b/hypervisor/arch/x86/timer.c index 42cf75712..7ae63ce06 100644 --- a/hypervisor/arch/x86/timer.c +++ b/hypervisor/arch/x86/timer.c @@ -221,7 +221,7 @@ void check_tsc(void) static uint64_t pit_calibrate_tsc(uint16_t cal_ms) { #define PIT_TICK_RATE 1193182UL -#define PIT_TARGET 0x3FFF +#define PIT_TARGET 0x3FFFU #define PIT_MAX_COUNT 0xFFFF uint16_t initial_pit; @@ -229,13 +229,13 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms) uint16_t max_cal_ms; uint64_t current_tsc; - max_cal_ms = (PIT_MAX_COUNT - PIT_TARGET) * 1000 / PIT_TICK_RATE; + max_cal_ms = (PIT_MAX_COUNT - PIT_TARGET) * 1000U / PIT_TICK_RATE; cal_ms = min(cal_ms, max_cal_ms); /* Assume the 8254 delivers 18.2 ticks per second when 16 bits fully * wrap. This is about 1.193MHz or a clock period of 0.8384uSec */ - initial_pit = (uint16_t)(cal_ms * PIT_TICK_RATE / 1000); + initial_pit = (uint16_t)(cal_ms * PIT_TICK_RATE / 1000U); initial_pit += PIT_TARGET; /* Port 0x43 ==> Control word write; Data 0x30 ==> Select Counter 0, @@ -261,7 +261,7 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms) current_tsc = rdtsc() - current_tsc; - return current_tsc / cal_ms * 1000; + return current_tsc / cal_ms * 1000U; } /* diff --git a/hypervisor/include/arch/x86/apicreg.h b/hypervisor/include/arch/x86/apicreg.h index 6f562c324..ef25e54b8 100644 --- a/hypervisor/include/arch/x86/apicreg.h +++ b/hypervisor/include/arch/x86/apicreg.h @@ -437,7 +437,7 @@ struct ioapic { */ /* default physical locations of an IO APIC */ -#define DEFAULT_IO_APIC_BASE 0xfec00000U +#define DEFAULT_IO_APIC_BASE 0xfec00000UL /* window register offset */ #define IOAPIC_WINDOW 0x10U diff --git a/hypervisor/include/arch/x86/ioapic.h b/hypervisor/include/arch/x86/ioapic.h index f32bfc294..ca7a104ed 100644 --- a/hypervisor/include/arch/x86/ioapic.h +++ b/hypervisor/include/arch/x86/ioapic.h @@ -11,7 +11,7 @@ * The usable RTEs may be a subset of the total on a per IO APIC basis. */ #define IOAPIC_MAX_LINES 120 -#define NR_LEGACY_IRQ 16 +#define NR_LEGACY_IRQ 16U #define NR_LEGACY_PIN NR_LEGACY_IRQ #define NR_MAX_GSI (CONFIG_NR_IOAPICS*IOAPIC_MAX_LINES)