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HV: link CONFIG_MAX_IOMMU_NUM and MAX_DRHDS to DRHD_COUNT 

The value of CONFIG_MAX_IOMMU and MAX_DRHDS are identical to DRHD_COUNT
which defined in platform ACPI table, so remove CONFIG_MAX_IOMMU_NUM
from Kconfig and link these three MACROs together.

Tracked-On: #3977

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Victor Sun 2019-10-29 17:13:58 +08:00 committed by wenlingz
parent 75f512ce8c
commit 589be88cf6
7 changed files with 14 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hypervisor/acpi_parser/dmar_parse.c
View File

@ -14,13 +14,13 @@
struct find_iter_args {
int32_t i;
uint32_t i;
struct acpi_dmar_hardware_unit *res;
};
typedef int32_t (*dmar_iter_t)(struct acpi_dmar_header*, void*);
static int32_t dmar_unit_cnt;
static uint32_t dmar_unit_cnt;
static void *get_dmar_table(void)
{
@ -72,7 +72,7 @@ drhd_find_iter(struct acpi_dmar_header *dmar_header, void *arg)
return 1;
args = arg;
if (args->i == 0) {
if (args->i == 0U) {
args->res = (struct acpi_dmar_hardware_unit *)dmar_header;
return 0;
}
@ -81,7 +81,7 @@ drhd_find_iter(struct acpi_dmar_header *dmar_header, void *arg)
}
static struct acpi_dmar_hardware_unit *
drhd_find_by_index(int32_t idx)
drhd_find_by_index(uint32_t idx)
{
struct find_iter_args args;
@ -229,7 +229,7 @@ handle_one_drhd(struct acpi_dmar_hardware_unit *acpi_drhd,
int32_t parse_dmar_table(struct dmar_info *plat_dmar_info)
{
int32_t i;
uint32_t i;
struct acpi_dmar_hardware_unit *acpi_drhd;
/* find out how many dmar units */
@ -238,12 +238,12 @@ int32_t parse_dmar_table(struct dmar_info *plat_dmar_info)
plat_dmar_info->drhd_count = dmar_unit_cnt;
for (i = 0; i < dmar_unit_cnt; i++) {
for (i = 0U; i < dmar_unit_cnt; i++) {
acpi_drhd = drhd_find_by_index(i);
if (acpi_drhd == NULL)
continue;
if (acpi_drhd->flags & DRHD_FLAG_INCLUDE_PCI_ALL_MASK)
ASSERT((i+1) == dmar_unit_cnt,
ASSERT((i + 1U) == dmar_unit_cnt,
"drhd with flags set should be the last one");
handle_one_drhd(acpi_drhd, &(plat_dmar_info->drhd_units[i]));
}

7
hypervisor/arch/x86/Kconfig
View File

@ -73,13 +73,6 @@ config MAX_PT_IRQ_ENTRIES
range 0 128
default 64
config MAX_IOMMU_NUM
int "Maximum number of IOMMU devices"
range 1 6
default 2
help
The maximum number of physical IOMMUs the hypervisor can support.
config STACK_SIZE
hex "Capacity of one stack, in bytes"
default 0x2000

1
hypervisor/arch/x86/configs/icl-rvp.config
View File

@ -3,4 +3,3 @@ CONFIG_BOARD="icl-rvp"
CONFIG_SERIAL_LEGACY=y
CONFIG_SOS_RAM_SIZE=0x600000000
CONFIG_UOS_RAM_SIZE=0x600000000
CONFIG_MAX_IOMMU_NUM=3

2
hypervisor/arch/x86/configs/platform_acpi_info.h
View File

@ -25,7 +25,7 @@
#define RESET_REGISTER_SPACE_ID 0UL
/* DRHD of DMAR */
#define DRHD_COUNT 0U
#define DRHD_COUNT 8U
#define DRHD0_DEV_CNT 0U
#define DRHD0_SEGMENT 0U

4
hypervisor/arch/x86/vtd.c
View File

@ -36,6 +36,8 @@
#define ROOT_ENTRY_LOWER_CTP_POS (12U)
#define ROOT_ENTRY_LOWER_CTP_MASK (0xFFFFFFFFFFFFFUL << ROOT_ENTRY_LOWER_CTP_POS)
#define CONFIG_MAX_IOMMU_NUM DRHD_COUNT
/* 4 iommu fault register state */
#define IOMMU_FAULT_REGISTER_STATE_NUM 4U
#define IOMMU_FAULT_REGISTER_SIZE 4U
@ -188,7 +190,7 @@ bool iommu_snoop_supported(const struct iommu_domain *iommu)
return ret;
}
static struct dmar_drhd_rt dmar_drhd_units[CONFIG_MAX_IOMMU_NUM];
static struct dmar_drhd_rt dmar_drhd_units[MAX_DRHDS];
static bool iommu_page_walk_coherent = true;
static uint32_t qi_status = 0U;
static struct dmar_info *platform_dmar_info = NULL;

54
hypervisor/boot/dmar_info.c
View File

@ -47,44 +47,6 @@ static struct dmar_dev_scope drhd1_dev_scope[MAX_DRHD_DEVSCOPES] = {
}
};
static struct dmar_dev_scope drhd2_dev_scope[MAX_DRHD_DEVSCOPES] = {
{
.bus = DRHD2_DEVSCOPE0_BUS,
.devfun = DRHD2_DEVSCOPE0_PATH
},
{
.bus = DRHD2_DEVSCOPE1_BUS,
.devfun = DRHD2_DEVSCOPE1_PATH
},
{
.bus = DRHD2_DEVSCOPE2_BUS,
.devfun = DRHD2_DEVSCOPE2_PATH
},
{
.bus = DRHD2_DEVSCOPE3_BUS,
.devfun = DRHD2_DEVSCOPE3_PATH
}
};
static struct dmar_dev_scope drhd3_dev_scope[MAX_DRHD_DEVSCOPES] = {
{
.bus = DRHD3_DEVSCOPE0_BUS,
.devfun = DRHD3_DEVSCOPE0_PATH
},
{
.bus = DRHD3_DEVSCOPE1_BUS,
.devfun = DRHD3_DEVSCOPE1_PATH
},
{
.bus = DRHD3_DEVSCOPE2_BUS,
.devfun = DRHD3_DEVSCOPE2_PATH
},
{
.bus = DRHD3_DEVSCOPE3_BUS,
.devfun = DRHD3_DEVSCOPE3_PATH
}
};
static struct dmar_drhd drhd_info_array[MAX_DRHDS] = {
{
.dev_cnt = DRHD0_DEV_CNT,
@ -102,22 +64,6 @@ static struct dmar_drhd drhd_info_array[MAX_DRHDS] = {
.ignore = DRHD1_IGNORE,
.devices = drhd1_dev_scope
},
{
.dev_cnt = DRHD2_DEV_CNT,
.segment = DRHD2_SEGMENT,
.flags = DRHD2_FLAGS,
.reg_base_addr = DRHD2_REG_BASE,
.ignore = DRHD2_IGNORE,
.devices = drhd2_dev_scope
},
{
.dev_cnt = DRHD3_DEV_CNT,
.segment = DRHD3_SEGMENT,
.flags = DRHD3_FLAGS,
.reg_base_addr = DRHD3_REG_BASE,
.ignore = DRHD3_IGNORE,
.devices = drhd3_dev_scope
}
};
static struct dmar_info plat_dmar_info = {

4
hypervisor/include/arch/x86/vtd.h
View File

@ -8,6 +8,8 @@
#define VTD_H
#include <types.h>
#include <pci.h>
#include <platform_acpi_info.h>
/*
* Intel IOMMU register specification per version 1.0 public spec.
*/
@ -468,7 +470,7 @@ static inline uint16_t dma_frcd_up_sid(uint64_t up_sid)
return ((uint16_t)up_sid & 0xffffU);
}
#define MAX_DRHDS 4
#define MAX_DRHDS DRHD_COUNT
#define MAX_DRHD_DEVSCOPES 4
#define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U